Cortex-A Series

Cortex-A Comparisons

All Cortex-A Processors share a common architecture and feature set.  This makes them the best solution for open platform design where compatibility and portability of software between design is of upmost importance:

• ARMv7-A architecture
• Support for full Operating Systems
  • Linux full distributions- Android, Chrome, Ubuntu and Debian
  • Linux 3rd party - MontaVista, QNX, Wind River
  • Symbian
  • Windows CE
  • Other OS support requiring Memory Management Unit
• Instruction Set Support - ARM, Thumb-2, Thumb, Jazelle®, DSP
• TrustZone^® Security Extensions
• Advanced single-precision and double-precision Floating Point support
• NEON™ media processing engine 

Together, the range of Cortex-A processor provide design flexibility by providing the required peak performance points and scalability and delivering the desired power efficiency and silicon cost while maintaining full software compatibility.

Cortex-A9

The Cortex-A9 processor is available as either a single-core or 1-4 core multicore synthesisable processor each offering 2.5 Dhrystone MIPS per MHz per CPU. In its single-core implementation an area optimized implementation of the processor provide a minimal footprint and exceptional energy efficiency for traditional embedded designs, while a speed optimized multicore implementation offers up to four time the total performance with the additional advantages of cache coherence, integrated peripherals and advanced bus interface options. 

A dual-core multicore solution is also available as a hard macro which can achieve over 2 GHz typical performance having leveraged the ARM high performance Physical IP within its implementation. 

Cortex-A9 processor benefits include:

• ARM's highest total performance platform with up to four cores operating in unison
• Leverages substantial multicore ecosystem with advanced OS support from major vendors
• Full scalability of solutions from minimal single-core through to MPCore™ with NEON

Cortex-A9 Hardmacro Implementations

The Cortex-A9 has also been hardened to the TSMC 40G/GL process as a fully configured dual-core hardmacro.  Offering performance over 2GHz when selected from typical silicon. These macro provide the silicon manufacturer a low-risk, and accellerated path to delivering the ARM low power solution for various high performance markets.

Cortex-A8

The Cortex-A8 processor is a dual-issue, in-order superscalar processor offering 2.0 Dhrystone MIPS per MHz targetted at highly optimized, power-efficient implementations that deliver the high-level performance required for a traditional single-processor based devices. The Cortex-A8 has established the ARMv7 architecture in the marketplace and is already available in diverse applications including smartphones, smartbooks, portable media players and other consumer and enterprise platforms.

The Cortex-A8 processor benefits include:

• A well-established eco-system including low-cost development platforms and available catalog parts
• Variety of licensing options for new entrants.
• Applications such as open source media players that can provide 720p video based on the NEON advanced SIMD instruction set.

Cortex-A5

The Cortex-A5 processor is the smallest, lowest power ARM multicore processor capable of delivering the Internet to the widest possible range of devices: from ultra low cost handsets, feature phones and smart mobile devices, to pervasive embedded, consumer and industrial devices.The Cortex-A5 processor is fully application compatible with the Cortex-A8  and Cortex-A9 processors, enabling immediate access to an established developer and software ecosystem including Android, Adobe Flash, Java Platform Standard Edition (Java SE), JavaFX, Linux, Microsoft Windows Embedded, Symbian and Ubuntu. Cortex-A5 benefits include:

• Full application compatibility with the Cortex-A8 and Cortex-A9 processors
• Provides a high-value migration path for the large number of existing ARM926EJ-S™ and ARM1176JZ-S™ processor licensees.

Cortex-A technologies

The Cortex-A processors share a number of key technologies that make them ideal for portable media-rich devices.

ARM MPCore™ Technology

The ARM MPCore technology allows for design-configurable processors supporting between one, two, three or four CPUs in operate in an integrated cache coherent manner.  These multicore processor clusters are fully coherent at the level-1 cache boundaries and in addition can be configured to extend limited coherency into the rest of the System on a Chip (SoC) through an Accelerator Coherence Port (ACP). The ACP permits system-mastering peripherals and accelerators with a non-cached view of memory, such as a DMA engine or cryptographic accelerator core, to share the processor caches in a fully cache coherent manner.  The multicore cluster includes a Global Interrupt Controller (GIC) architecture compliant integrated interrupt and communication system with private peripherals for increased performance and simplified software portability.  This GIC can be configured to support between 0 (legacy bypass mode) to 224 independent interrupt sources providing a low latency interrupt path to a large number of devices.  The processor can support either a single or dual 64-bit AMBA® 3 AXI™ interconnect interface with the option for full speed filtering between different address space within the SoC.

The intelligence of the MPCore technology comes from the Snoop Control Unit (SCU) which  is responsible for managing the interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence and other multicore capabilities for all MPCore technology enabled processors.  

ARM MPCore technology allows for very efficient, scalable multi-processing CPU clusters which give a very high-range of performance possibilities with very low software overhead. In Symmetric Multi-Processing (SMP) mode, the OS scheduler handles all allocation of threads to the processing cluster making it transparent to applications running. Most current high-level operating systems have built-in support for this mode of operation.