Infrastructure for Next-Generation Throughput Demands

The Neoverse E1 processor is a new class of highly efficient CPU technology designed specifically for throughput compute workloads. The design is highly scalable to support throughput demands for next generation edge to core data transport.

Features and Benefits

Highly Efficient Throughput

Simultaneous multithread (SMT) enables Neoverse E1 to execute two threads concurrently resulting in improved aggregate throughput performance. The out-of-order pipeline increases overall performance and offers greater efficiency over its predecessors.

Arm Software Ecosystem

By supporting the Armv8.2-A architecture and AArch64 ISA, Neoverse E1 is compatible with Neoverse N1, and leverages a broad ecosystem, from tools to OS and application support (e.g. Linux kernel, Data Plane Development Kit and OpenSSL libraries).

Highly Scalable Platform

Neoverse E1 is a flexible platform which supports scalability from 25Gbps in 4W CPU power budget to multi-100Gbps systems. Accelerator Coherency Port (ACP) enables closely coupled fixed-function hardware offload support with low latency and cache stashing capability.

Neoverse E1 CPU Specs


The Neoverse E1 processor is a new class of highly efficient CPU designed specifically for throughput compute workloads.

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Key Documentation

Related Products and Tools

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Arm’s Big Opportunity to Expand into Datacenter Infrastructure

The first extensive CPU core roadmap from Arm, Neoverse is aimed specifically at infrastructure, as distinct from consumer IP lines. It comes in the wake of significant signs of traction for the firm in the systems and cloud infrastructure space.

Arm SystemReady: A Compliance Program for Arm-based Servers

Simplify out-of-the-box deployment using a common set of principles that software developers and customers can rely on.

The Arm Neoverse E1 Platform is Empowering the Infrastructure to Meet Next-Generation Throughput Demands

The microarchitecture for Neoverse E1 was developed around two design goals: maximizing throughput while balancing compute and efficiency requirements.