Highly Scalable Mesh for Intelligent Connected Systems
The Arm CoreLink CMN-600 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points.
The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.
Socrates guides designers through the configuration and creation of an optimized and viable CoreLink CMN-600 interconnect fabric. By addressing complex challenges associated with Interconnect configurability and assembly, it helps speed design time and produce a higher quality interconnect.
The CoreLink CMN-600 and CoreLink DMC-620 provide the highest performance coherent backplane for Armv8-A systems from small, efficient access points to data center solutions maximizing compute density.
CoreLink CMN-600 coherent multichip links (CML) extend the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, so system designers can attach more compute or acceleration with a shared virtual memory.
The multichip links also support CCIX, the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices.
Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache is designed to boost IO throughput workloads, such as networking and storage.
Looking to build more powerful infrastructure SoCs from edge to cloud? Find out how the Arm CoreLink CMN products can help.
Arm processors range from ultra-low power Cortex-M series to server-class Cortex-A series.
Graphics and Multimedia
Arm Mali media IP offer high-performing, energy-efficient media processing across a large and growing number of mobile and consumer devices, including smartphones, tablets, TVs and wearables.
CoreSight Debug and Trace
Arm CoreSight technology is a set of tools that can be used to debug and trace software that runs on Arm-based SoCs.
The Arm family of Dynamic Memory Controllers manage the differing demands of multiple processing elements while delivering maximum DRAM bandwidth.
System Memory Management Units
A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization.
Arm generic interrupt controllers (GIC) perform critical tasks of interrupt management, prioritization and routing.
Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.