Fastest Path to Production Silicon with World-Leading Performance, on Leading-Edge Technology
Pressure on today’s computing infrastructure is driving the need for specialized processing across cloud, AI, 5G, and networking markets. With Arm Neoverse Compute Subsystems (CSS), Arm delivers validated, performance-optimized compute on a leading-edge foundry process, so Arm’s infrastructure partners can focus scarce silicon design resources on building differentiated, market-customized solutions.
Features and Benefits
With Arm Neoverse Compute Subsystems (CSS), Arm delivers a proven, verified compute subsystem that can reduce risk, lower NRE, and accelerate CPU time to market by up to one year. Together with SystemReady SR compliance, Neoverse CSS helps enable a software ecosystem that just works.
Neoverse CSS takes Arm Neoverse platform IP and optimizes it for performance, power, and area using a leading-edge foundry process. Customers can customize Neoverse CSS with on-chip or off-chip accelerators for performance-per-watt optimized specialized computing.
Neoverse CSS delivers the roadmap of Armv9 features and Neoverse technologies out of the box – Arm Confidential Compute, AMBA CHI C2C, Arm Scalable Matrix Extensions, and more. Neoverse CSS also provides system management, power management, and platform software support.
Neoverse CSS Customer Value
Arm Neoverse CSS delivers customer value by performing more of the non-differentiated but necessary steps in bringing customized silicon to market. Neoverse CSS customers have reported significant benefits from this unique engagement with Arm, including:
Months from Kick-off to Working Silicon
Engineering Years Saved
Components of a Neoverse Compute Subsystem
Arm Neoverse Compute Subsystems include Neoverse cores, CMN mesh, and system IP, as well as system management, power management, software and development tools needed to deliver performance-optimized compute to market quickly.
Explore More Products and Tools
Our first Armv9 infrastructure CPU, Neoverse N2 offers best-in-class performance, efficiency, and compute density, while maintaining the cloud-native experience.
The highly scalable mesh is optimized for Armv9 and Armv8-A processors, multichip configurations, and CXL attached devices. It can be customized across a wide range of performance points.
Arm SMMU v3.2 compliant MMU-700 is compatible with Arm v8.4 and v9 CPU’s. It enables virtualization in the Arm Secure World and QoS for IO traffic. MMU-700 is built for PCIe Gen5 BW.
A scalable and highly configurable packetized network-on-chip (NoC) with a 30 percent wire count reduction compared to a traditional crossbar. Supports multiple clock and power domains and up to 1GHz+ operation.
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