Neoverse CSS N2: The Arm Neoverse N2 Platform, Delivered to Partners as a Verified, Performance-Validated Customizable Subsystem
Arm Neoverse CSS N2 is the first generation of Neoverse CSS products designed to speed time to production silicon, deliver world-class performance, and bring leading-edge technology to the Arm ecosystem. CSS N2 packs up to 64 Neoverse N2 cores, with DDR5 memory and PCIe Gen5/CXL I/O, into a performance- and power-optimized subsystem.
Features and Benefits
CSS N2 partners report significant benefits, such as advancing from design idea to working silicon in 13 months and saving an estimated 80 engineering years of design effort. CSS N2 lets partners get to market faster than ever and allows design resources to focus on building specialized silicon.
CSS N2 delivers an estimated SPECrate® 2017 integer score of 1000 when configured in a multichip system with an aggregate of 256 Arm Neoverse N2 cores at 3.0GHz.
CSS N2 implements the latest memory and I/O technologies, including DDR5/LPDDR5, PCIe Gen5, and CXL, on an advanced 5nm fabrication process.
Performance that Spans Cloud to Edge
Cloud customers are experiencing up to 40% improved price performance over comparable traditional architecture-based instances on a broad range of workloads.
To deliver on performance and versatility, 5G requires a more complex and robust infrastructure. Arm delivers technology for building faster, low-latency 5G networks.
Explore More Options and Features
Our first Armv9 infrastructure CPU, Neoverse N2 offers best-in-class performance, efficiency, and compute density, while maintaining the cloud-native experience.
The highly scalable mesh is optimized for Armv9 and Armv8-A processors, multichip configurations, and CXL attached devices. It can be customized across a wide range of performance points.
Arm SMMU v3.2 compliant MMU-700 is compatible with Arm v8.4 and v9 CPU’s. It enables virtualization in the Arm Secure World and QoS for IO traffic. MMU-700 is built for PCIe Gen5 BW.
GIC-700 hardware accelerates virtual interrupts to be delivered to virtual machines providing significant system performance improvement over Arm CoreLink GIC-600.
A scalable and highly configurable packetized network-on-chip (NoC) with a 30 percent wire count reduction compared to a traditional crossbar. Supports multiple clock and power domains and up to 1GHz+ operation.