Highly Configurable Topology for SoC Connectivity
The Arm CoreLink Network Interconnect is configurable across a wide range of applications, from a single bridge component to a complex infrastructure.
Features and Benefits
Highly configurable low latency IP that can be optimized to suit the requirements of a complex SoC using the AMBA protocols.
Including AXI4, AXI3, AHB-Lite and APB. Connectivity to cache coherent systems is supported with the CoreLink CCI family
A wide configuration space and flexible topology allows Corelink NI-700 to scale from a simple one-input one-output bridge, all the way up to an SoC-wide interconnect with over 100 interfaces.
CoreLink Network Interconnect Family
A scalable and highly configurable packetized Network-on-Chip (NoC) with a 30 percent wire count reduction compared to a traditional crossbar. Supports multiple clock and power domains and up to 1GHz+ operation.
Fully configurable, hierarchical, low latency, low power connectivity for AMBA 4 AXI4, AXI3, AHB-Lite and APB interfaces. Also, scalable for multiple applications from simple single core designs or as a companion to CoreLink CCI and CCN coherent interconnects.
Includes NIC-400 features, plus a library of key interconnect IP for building a scalable and configurable network interconnect, and tooling automation flow using CoreLink Creator to accelerate configuration, and more.
With its harvesting flows and enhanced tooling environment, CoreLink Creator provides significant improvements to configure NICs to decrease time to market.
Where Innovation and Ideas Come to Life
Computational storage, also known as in-situ processing or in-storage compute, is an example of a smart storage application that benefits from the flexible, low-latency, low-power connectivity offered by the CoreLink Network Interconnect family.
Talk with an Expert
Still unsure which CoreLink CCN product is right for your SoC project? Talk to an Arm expert and learn more.
Explore More Options and Features
Cloud service providers, carriers, system designers and others are turning to Arm Neoverse to build 5G networks, hyperscale datacenters, and high performance computing (HPC) systems. Arm Neoverse delivers leading performance and scalability while dramatically reducing power consumption and total cost of ownership (TCO).
CoreLink Cache Coherent Interconnect
Hardware-managed cache coherency is required to enable big.LITTLE processing to choose the right processor for the right job. The Arm CoreLink CCI series has been designed into many applications, including mobile, tablet, digital TV, set top box, automotive, and low-cost infrastructure.
Arm processors include the ultra-low power Cortex-M series, real-time response Cortex-R series, and the server-class Cortex-A series.
System Memory Management Units
A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization.
Arm generic interrupt controllers (GIC) perform critical tasks of interrupt management, prioritization and routing.
CoreLink Network Interconnect Resources
Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.