Highly Configurable Topology for SoC Connectivity
The Arm CoreLink Network Interconnect offers highly configurable topology with network-on-chip type properties for building high-performance, optimized, AMBA-compliant SoC connectivity. CoreLink Network Interconnect is configurable across a wide range of applications, from a single bridge component to a complex infrastructure.
The CoreLink Network Interconnect is a highly configurable low latency IP that can be optimized to suit the requirements of a complex SoC using the AMBA protocols.
Interfaces are fully configurable between AXI4, AXI3, AHB-Lite and APB. Connectivity to cache coherent systems is supported with the CoreLink CCI and CCN families.
The CoreLink NIC-400 can be used together with the CoreLink CCN-504 Cache Coherent Network or the CoreLink CCI-400 Cache Coherent Interconnect to extend I/O coherency to larger numbers of masters.
A wide configuration space and flexible topology allows the interconnect to adapt to the system requirements and SoC floor plan. The product can scale from a simple one input one output bridge, all the way up to an SoC wide interconnect with over 100 interfaces.
Fully configurable, hierarchical, low latency, low power connectivity for AMBA 4 AXI4, AXI3, AHB-Lite and APB interfaces. Also, scalable for multiple applications from simple single core designs, up to large coherent systems as a companion to CoreLink CCI and CCN coherent interconnects.
All CoreLink NIC-400 features, plus a library of key interconnect IP for building a scalable and configurable network interconnect, and tooling automation flow using CoreLink Creator to accelerate configuration, and more.
CoreLink Creator with its harvesting flows and enhanced tooling environment provides significant improvements to configure NICs, which decreases time to market. It is included in CoreLink NIC-450.
Still unsure which CoreLink CCN product is right for your SoC project? Talk to an Arm expert and learn more.
CoreLink Cache Coherent Interconnect
Hardware-managed cache coherency is required to enable big.LITTLE processing to choose the right processor for the right job. The Arm CoreLink CCI series has been designed into many applications, including mobile, tablet, digital TV, set top box, automotive, and low-cost infrastructure.
Corelink Cache Coherent Network
The Arm CoreLink CCN family scales across the performance spectrum supporting from 1 to 48 cores along with an integrated, configurable Level 3 system cache.
Arm processors include the ultra-low power Cortex-M series, real-time response Cortex-R series, and the server-class Cortex-A series.
The Arm family of Dynamic Memory Controllers manage the differing demands of multiple processing elements while delivering maximum DRAM bandwidth.
System Memory Management Units
A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization.
Arm generic interrupt controllers (GIC) perform critical tasks of interrupt management, prioritization and routing.
CoreLink Network Interconnect Resources
Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.