Industry-leading Performance and Power Efficiency for Cloud-to-Edge Infrastructure

Our first Armv9 infrastructure CPU, Neoverse N2 offers best-in-class performance, efficiency, and compute density, while maintaining the cloud native experience.

Features and Benefits

Cloud-to-Edge Scalability

Market-leading scalability and versatility that addresses a wide range of workloads from scale-out cloud to edge compute. In high core-count cloud applications, chip designers can deliver more than 128 threads per socket.

Performance for 5G and Scale-Out Cloud

A significant 40 percent performance increase over the Neoverse N1 CPU along with industry-leading power and area efficiency, and single-thread performance for scale-out cloud and 5G applications. 

Armv9 Features for Infrastructure

Uses Armv9 CPU for infrastructure and introduces key features for performance, power efficiency, and security: Scalable Vector Extension (SVE) version two (SVE2) and Memory Tagging Extension (MTE).

Product Specifications and Key Documentation

 Architecture  Armv9.0-A (Harvard)  
 Extensions  Armv8.4
  • Scalable Vector Extensions
  • MPAM
  • Enhanced Nested Virtualization
  • Enhanced Cryptography
  • RAS Extensions
  • PMU Extensions
  • Secure EL2
  • TLB Maintenance Ops
  • Small page tables
  • Flag Manipulation
 Armv8.5
  • FP to Int
  • Enhanced Virtualization traps
  • BTI
  • Speculation control
  • Enhanced PMU
 Armv8.6
  • Enhanced Pointer Authentication
 Armv9
  • SVE2
  • Enhanced cryptography instructions
  • Embedded Trace Extension
  • Self-hosted Trace
 
 ISA support
  • A32 and T32 (at the EL0 only)
  • A64
 
 Microachitecture  Pipeline  Out-of-order
 Superscalar  Yes
 SVE2/ Neon / Floating Point Unit  Included
 Cryptography unit  Optional
 Max number of CPUs in cluster  Direct-connect
 Physical addressing (PA)  48-bit
 Memory system and external interfaces  L1 I-Cache /D-Cache  64KB
 L2 Cache  1MB or 512kB
 ECC support  Yes
 LPAE  Yes
 Bus interfaces  AMBA CHI
 Other  Security  TrustZone
 Interrupts  GIC interface, GICv3 and GICv4
 Generic timer  Armv8-A
 PMU  PMUv3.4
 Debug  Armv9-A (plus Armv8.2-A extensions)
 CoreSight  CoreSightv3
 Embedded Trace Macrocell  ETMv4.2 (instruction trace)

Key documentation
Industry Solutions 

Performance that Spans Cloud to Edge

5G

To deliver on performance and versatility, 5G requires a more complex and robust infrastructure. Arm delivers technology for building faster, low-latency 5G networks.

Cloud Computing

Cloud customers are experiencing improved price performance over comparable traditional architecture-based instances on a broad range of workload.

Edge Computing

The combination of leading performance with incredible power efficiency makes Neoverse N2 the perfect solution for power and space constrained edge use cases.

System IP Configurable for Many Applications

CMN-700

The highly scalable mesh is optimized for Armv9 and Armv8-A processors, multi-chip configurations, and CXL attached devices. It can be customized across a wide range of performance points. 

MMU-700

Arm SMMU v3.2 compliant MMU-700 is compatible with Arm v8.4 and v9 CPU’s. It enables virtualization in the Arm Secure World and QoS for IO traffic. MMU-700 is built for PCIe Gen5 BW.

GIC-700

GIC-700 hardware accelerates virtual interrupts to be delivered to virtual machines providing significant system performance improvement over Arm CoreLink GIC-600.

Talk with an Expert

Reach out to our experts for answers and resources on how to leverage Neoverse N2 to create highly differentiated revolutionary system solutions.

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Resources