ARM-Cadence Encounter Reference Methodology
Optimized RTL-to-GDSII implementation flow for ARM synthesizable processors

With the increasing use of ARM synthesizable processors for leading-edge designs, customers want integrated solutions to achieve highest quality-of-silicon with the fastest design cycle. ARM licensees need the predictability and time-to-market advantages of a hardened processor with the flexibility of a fully synthesizable implementation. By streaming the implementation of ARM synthesizable processors, the ARM-Cadence Encounter Reference Methodology provides this capability and is a key deliverable of the ongoing collaboration between ARM and Cadence.

The ARM-Cadence Encounter Reference Methodology is a proven implementation flow that delivers a powerful, deterministic, and rapid route from RTL to GDSII for ARM synthesizable processors. This increases the productivity of the design team and reduces time-to-silicon with predictable performance, power, and area results. In addition, by providing accurate abstract models, the methodology enables licensees to deploy the ARM processor as a library component for System-on-Chip (SoC) integration by end users.

This RTL-to-GDSII flow is based on the Cadence Encounter digital IC design platform. The Cadence tools supported in the ARM-Cadence Encounter Reference Methodology include Encounter RTL Compiler, First Encounter, NanoRoute, Fire & Ice QXC, CeltIC NDC, VoltageStorm and Encounter Conformal Logic Equivalence Checker.

ARM and Cadence are committed to maintaining Reference Methodologies in line with tool enhancements by Cadence and release of new synthesizable processors from ARM.