*
*Home|Chinese|Japanese*About ARM|Forums|Events|News|Employment|Contact Us|Investors*
dotted rule
*ARM - the architecture for the digital worldARM - the architecture for the digital world
search
*
*
***
*MARKETS:PRODUCTS & SOLUTIONS:CONNECTED COMMUNITY:TECHNICAL SUPPORT:DOCUMENTATION*
*
products and solutions
*
*
****
*.Products & Solutions
*
*
 >>Home Page 
*
 .Consultancy 
*
 .RealView Development Tools 
*
 .Fabric IP 
*
 .Graphics Solutions 
*
 .On-chip Debug & Trace 
*
 .Physical IP 
*
 .Processors 
*
  Processor Overview 
*
  Processor Selector 
*
 .Processor Families 
*
   
.
   
.
   
.
   
.
   
.
  ARM9E 
.
   
.
  Processor Architecture 
*
  Reference Methodology 
*
  Performance Packages 
*
  Application Processors 
*
  Embedded Processors 
*
*
 .Security Solutions 
*
 .Operating System Support 
*
 .Licensing 
*
 >>Markets 
*
 >>Books 
*
*
*

ARM9E Family

ask ARM*
*

ARM926EJ-S , ARM946E-S, ARM966E-S, ARM968E-S and ARM996HS

The ARM9E processor family enable single processor solutions for microcontroller, DSP and Java applications, offering savings in chip area and complexity, power consumption, and time-to-market. The ARM9E family of products are DSP-enhanced 32-bit RISC processors, well suited for applications requiring a mix of DSP and microcontroller performance. The family includes the ARM926EJ-SARM946E-SARM966E-SARM968E-S and ARM996HS processor macrocells, each of which has been developed to address different application requirements. They include signal processing extensions to enhance 16-bit fixed point performance using a single-cycle 32 x 16 multiply-accumulate (MAC) unit, and implement the 16-bit Thumb® instruction set giving excellent code density, maximising savings on system cost. The ARM926EJ-S processor also includes ARM Jazelle™ technology which enables the direct execution of Java bytecodes in hardware.

  • Jazelle technology, memory management unit (MMU), variable size instruction and data caches (4K - 128K), instruction and data tightly coupled memory (TCM) interfaces
  • Variable size instruction and data cache (0K- 1M), instruction and data TCM(0 - 1M), and memory protection unit for embedded applications.
  • Targets "hard real-time" applications requiring predictable instruction execution timings with high performance and low power consumption.
  • The smallest, lowest power ARM9E family processor to date, aimed specifically at embedded real-time applications.
  • MOVE Video Coprocessor. This coprocessor for ARM9E family processors accelerates the Sum of Absolute Differences (SAD) operation used in MPEG-4 Encoder Motion Estimation.

Applications

  • Next-generation hand-held products
    – Videophones, portable communicators, Internet appliances
  • Digital consumer products
    – Set-top boxes, home gateways, games consoles,
  • Imaging
    – Desktop printers, still picture cameras, digital video cameras
  • Storage
    – HDD and DVD drives
  • Automotive
    – Powertrain, infotainment, ABS, body control systems
  • Industrial control systems
    – Motion controls, power delivery
  • Networking
    – VoIP, Wireless LAN, xDSL

ARM9E Family

  • 32-bit RISC processor with ARM®, Thumb® and DSP instruction sets
  • ARM Jazelle technology delivers 8x Java acceleration (ARM926EJ-S)
  • 5-stage integer pipeline achieves 1.1 MIPS/MHz
  • Up to 300 MIPS (Dhrystone 2.1) in a typical 0.13µm process
  • Integrated real-time trace and debug support
  • Optional VFP9 coprocessor delivers floating-point performance
  • 215 MFLOPS for 3D graphics and real-time control systems
  • High-performance AHB system
  • MMU supporting Windows CE, Symbian OS, Linux, Palm OS (ARM926EJ-S)
  • Integrated instruction and data caches
  • Real-time debug support for SoC designers, including ETM interface
  • 16-entry write buffer — avoids stalling the processor when writes to external memory are performed
  • Flexible soft IP delivery, synthesizable to the latest 0.18µm, 0.15µm, 0.13µm silicon processes.

For a list of public ARM9 licensees, click here

*

**
*4 dots*Other ARM Websites | Help with Accessibility
*
shadow *LEGAL STATEMENTshadow