ARM1026EJ-S High Performance, Jazelle-enhanced Macrocell

The ARM1026EJ-S macrocell is a fully synthesizable processor delivering a high level of performance, functionality and flexibility to enable innovative SoC applications. A Jazelle Technology enhanced 32-bit RISC ARM10EJ-S CPU with extensive 64-bit internal bussing is combined with configurable instruction and data caches, configurable tightly coupled memories (TCM), support for parity protection on SRAM arrays, memory management and protection units (MMU and MPU), vector interrupt controller interface, advanced vector floating point support and dual 64/32-bit configurable AMBA AHB system interfaces. The ARM1026EJ-S core implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution.

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• Hand-held products
  • internet appliances, portable communicators and PDAs
• Digital consumer products
  • set-top boxes, home gateways, VoIP telephones, web tablets, laser printers, game consoles, digital cameras and TV
• Automotive control systems
  • powertrain control, drive-by-wire control, infotainment and navigation
• Industrial control systems
  • motion controls, power delivery and signal processing

Features:

• 32-bit performance-optimized processor core implementing the ARM, Thumb, DSP, and Java ISAs (v5TEJ)
     - Highly-efficient ARM10EJ-S core achieves 1.35 MIPS/MHz on Dhrystone 2.1 without inlining
     - Extensive 64-bit internal bussing delivers increased bandwidth for applications with large working sets
• Full MMU support for Windows CE, Linux, Palm OS, Symbian OS, and Java OS
• Full MPU support for a broad range of real time operating systems
• Separate instruction and data caches
     - Configurable sizes (4 – 128kB) with 4 way associativity  
• Separate instruction and data TCM
     - Configurable sizes (0 – 1MB) and support for wait state insertion  
• Parity protection support on SRAM arrays for maximum field reliability
• Dual 64 or 32-bit AMBA AHB bus interfaces
• Direct-attach vector interrupt controller interface for improved interrupt response
• Support for optional vector floating point and embedded trace coprocessors
• EmbeddedICE-RT logic for real-time debug
• Fully-synthesizable and process portable design delivered as RTL

Benefits:

• Flexible, high-performance, low-power core for innovative SoC applications
• Runs all major OSs and existing middleware
• Enables low-cost, single-chip MCU, DSP, and Java solutions
• High-performance hardware Java bytecode execution
• Single development toolkit for reduced development costs and shorter development cycle time
• Synthesizable design allows sourcing from multiple industry-leading silicon vendors
• Excellent real-time debug support for SoC designers via optional ETM10RV macrocell macrocell
• Instruction set can be extended by the use of coprocessors
• ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.

		Cache Size (Inst/Data)	Tightly Coupled Memory	Memory Mgt	Bus Interface	Thumb	DSP	Jazelle
	ARM1026EJ-S	Variable	Yes	MMU or MPU	2x AHB	Yes	Yes	Yes

			0.13	90 nm
			Speed Opt	Speed Opt	Area Opt
	Standard Cells		-	Advantage-HS	Metro
	Memories		-	Advantage	Metro
	Frequency* (MHz)		266	540	280
	Area with cache (mm²)		4.20	2.45	1.45
	Area without cache (mm²)		2.70	1.90	0.95
	Cache Size		8K/8K	8K/8K	8K/8K
	Power with cache† (mW/MHz)		1.05	0.45	0.25
	Power w/o cache† (mW/MHz)		0.60	0.40	0.18

1. Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs.
2. The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.
3. The cache sizes are specified as InstructionCache/DataCache. The area w/o cache numbers quoted exclude RAM area, but include all logic including memory management, cache control and debug. The area with cache numbers quoted includes the core, the specified instruction and data caches and all necessary RAMs.
4. * Worst case conditions – 0.13µm process - 1.08V, 125C, slow silicon ; 90nm process - 0.9V, 125C, slow silicon
5. † Typical case conditions – 0.13µm process - 1.2V, 25C, typical silicon ; 90nm process - 1V, 25C, typical silicon