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ARM Cortex-A8

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The ARM CortexTM-A8 processor is the first applications processor based on the ARMv7 architecture and is the highest performance, most power-efficient processor available from ARM. With the ability to scale in speed from 600MHz to greater than 1GHz, the Cortex-A8 processor can meet the requirements for power-optimized mobile devices needing operation in less than 300mW; and performance-optimized consumer applications requiring 2000 Dhrystone MIPS.  
The Cortex-A8 processor is ARM’s first superscalar processor featuring  technology for enhanced code density and performance,  NEON™ technology for multimedia and signal processing, and Jazelle® RCT (Runtime Compilation Target) technology for efficient support of ahead-of-time and just-in-time compilation of Java and other bytecode languages. 

 Cortex A-8 Chip Diagram - Click to Enlarge

Enlarge Diagram

The exceptional speed and power efficiency of the Cortex-A8 processor is enabled by new ARM Artisan® Advantage-CE libraries supporting  and implementing advanced leakage control.

The processor is supported by a wide range of ARM technologies for rapid system design including:

Architectural Features:
The ARM Cortex-A8 processor’s sophisticated pipeline architecture is based on dual, symmetric, in-order issue, 13-stage pipelines with advanced dynamic branch prediction achieving 2.0 DMIPS/MHz. 

  • In-order, dual-issue, superscalar microprocessor core
    • 13-stage main integer pipeline
    • 10-stage NEON media pipeline
    • Dedicated L2 cache with programmable wait states
    • Global history based branch prediction
  • Works in conjunction with a power optimized load store pipeline to deliver 2.0 DMIPS/MHz for power sensitive applications
  • ARMv7 architecture compliant including:
    • Thumb®-2 technology for greater performance, energy efficiency, and code density
    • NEON™ signal processing extensions to accelerate media codecs such as H.264 and MP3
    • Jazelle RCT Java-acceleration technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC), and reduce memory footprint by up to three times
    • TrustZone technology for secure transactions and Digital Rights Management (DRM)
  • Integrated Level 2 Cache
    • Built using standard compiled RAMs
    • configurable size from 0K – 1MB
    • Programmable delay
  • Optimized Level 1 Caches
    • Performance and power optimized
    • Combine minimal access latency with hash way determination to maximize performance and minimize power consumption.
  • Dynamic Branch Prediction
    • Enabled by branch target and global history buffers
    • Achieves 95% accuracy across industry benchmarks.
    • Replay mechanism minimizes miss-predict penalty
  • Memory System
    • Single-cycle load-use penalty for access to the L1 cache
    • Hash array in the L1 cache limits activation of the memories to when they are likely to be needed.
    • Direct interface between the integrated, configurable L2 cache and the NEON media unit for data streaming
    • Banked L2 cache design that enables only one bank at a time
    • Support for multiple outstanding transactions to the L3 memory to fully utilize the CPU

Related Links:

 

 

 

Performance Characteristics
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*65 nm
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*Process 65nm (LP)65nm (GP)
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*Frequency* (MHz) 650+1100+
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*Area with cache (mm²) <4<4
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*Area without cache (mm²) <3<3
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*Power with cache† (mW/MHz) <0.59<0.45
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Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of cores implemented using general purpose TSMC process technologies and ARM Artisan Advantage-HS standard cell libraries and Advantage optimized RAM components.

All area figures include L2 cache control logic but exclude NEON, ETM and L2 cache RAMs.  “Area with cache” figures are for the core with 32Kx32K L1 cache.

The 65nm (LP) dynamic power measured is at 1.2 V nominal and hence is higher than the 65nm(GP) dynamic power which is at 1.0V. However, the 65nm (LP) leakage is significantly lower and this is the major consideration for mobile or battery operated devices which need to conserve power in standby mode.

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