| The ARM Cortex-A9 processor provides unprecedented levels of performance and power efficiency making it an ideal solution
for any design requiring high performance in a low-power, cost sensitive, single processor-based device. Using a convenient
synthesizable flow and IP deliverables, the Cortex-A9 processor provides an ideal upgrade path for existing ARM11™ processor-class
designs that require higher performance and increased levels of power efficiency within a similar silicon cost and power budget
while maintaining a compatible software environment.
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The Cortex-A9 single core processor provides dual low-latency Harvard 64-bit AMBA® 3 AXI™ master interfaces for independent
instruction and data transactions and are capable of sustaining four double word writes every five processor cycles when copying
data across a cached region of memory.
Both the Cortex-A9 and Cortex-A9 MPCore processors provide a scalable solution across a wide range of market applications from mobile handsets through to high-performance
consumer and enterprise products by sharing the common requirements of:
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Increased power efficiency with higher performance for lower power consumption
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Increased peak performance for most demanding applications
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Ability to share software and tool investments across multiple devices
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Feature
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Benefit
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High-Efficiency Superscalar Pipeline
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Industry leading performance with over 2.0 DMIPS/MHz for unprecedented peak performance while also maintaining low power
for extended battery life and lower cost packaging and operation
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| NEON Media Processing Engine |
Accelerating media and signal processing functions for increased application specific performance with the convenience of
consolidated application software development and support
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Floating-Point Unit
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Provides significant acceleration for both single and double precision scalar Floating-Point operations. Double the performance
of previous ARM FPU, this unit provides industry leading image processing, graphics and scientific computation capabilities
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Optimized Level 1 Caches
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Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power
consumption. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP
capable OS for simplified multicore software development
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Thumb®-2 Technology
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Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store
instructions
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TrustZone® Technology
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Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad
support from technology and industry Partners
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Jazelle® RCT and DBX Technology
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Provides up to 3x reduction on code size for Just-in-time (JIT) and ahead-of-time compilation of bytecode languages while
also supporting direct byte code execution of Java instructions for acceleration in traditional virtual machines
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| L2 Cache Controller |
Providing low latency and high bandwidth access to up to 2 MB of cached memory in high frequency designs, or design needing
to reduce the power consumption associated with off chip memory access
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Program Trace Macrocell and CoreSight™ Design Kit
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Together these components provide the software developer with the ability to non-obtrusively trace the execution history of
multiple processors and either store this, along with time stamped correlation, into an on-chip buffer, or off chip through
a standard trace interface so as to have improved visibility during development and debug
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For 2000 DMIPS of performance when designed in a TSMC 65 nanometer (nm) generic process the core logic costs less than 1.5
mm2 of silicon. In addition, the Cortex-A9 processors are fully application compatible and can further enhance application
specific performance by utilizing either the Cortex-A9 NEON™ Media Processing Engine or the Cortex-A9 Floating-Point Unit
to further extend the scope of solutions utilizing this processor.
COMPLETE SYSTEM SOLUTION Both ARM Cortex-A9 processors include ARM’s application specific architecture extensions, including DSP and SIMD extensions,
Jazelle technology, TrustZone technology and Intelligent Energy Manager (IEM™) technology. In addition, ARM has developed
a full range of supporting technology around the new processor to reduce design time and accelerate time-to-market. This complete
system solution comprises fabric IP, system design, development and debug tools, and ARM AdvantageTM standard cell libraries and memories.
- Floating-Point Unit (FPU): The Cortex-A9 FPU provides high-performance single and double precision floating-point instructions.
- Media Processing: The Cortex-A9 NEON Media Processing Engine (MPE) offers the performance and functionality of the Cortex-A9
FPU plus the ARM NEON Advanced SIMD instruction set first introduced with the Cortex-A8 processor for accelerated media and
signal processing functions.
- Physical IP: Providing a wide range of products including standard cell libraries and memories required for low-power and high-performance implementations on a Cortex-A9 processor. The standard cells include
power management kits that enable dynamic and leakage power saving techniques such as clock gating, multi-voltage islands
and power gating. The memory compilers are also offered with advanced power-saving features. The Physical IP products, which are immediately available for download
at access.arm.com, can be used for both single and multicore implementations.
- Fabric IP: The Cortex-A9 processor is supported by a comprehensive set of PrimeCell® fabric IP components including the PL341 DDR2 dynamic memory controller, the PL351 static memory controller, plus the PL301
AXI configurable interconnect. In addition, the PL310 L2 Cache Controller has been developed to provide an optimized L2 cache
controller that can match the performance and throughput capability of the Cortex-A9 processors in high frequency designs.
The AMBA® Designer tool enables SoC developers to configure and stitch complex AXI interconnect sub-systems and export RTL to standard
EDA flows.
- System Design: The RealView System Generator tool offers ultra-fast modelling capability for deployment of Cortex-A9 processor-based virtual platforms running native
ARM code to large communities of software developers. Cycle based and programmers’ view models of the Cortex-A9 processor,
for use in RealView tools, will be available in 2Q 2008.
- Debug: The Cortex-A9 processor uses ARM CoreSight technology to speed complex debug and reduce time-to-market. The processor includes Program Trace Macrocell technology to enable program-flow
trace capabilities for full visibility into the processor’s instruction flow, and implements the ARMv7 architecture-compliant
debug interface to enable tools standardization and higher debug performance. The available CoreSight design kit for the Cortex-A9
processor extends the debug and trace capability to cover the entire system-on-chip including multiple ARM processors, DSPs,
and intelligent peripherals.
- Software Development: The ARM RealView Development Suite includes advanced code generation tools which will implement Cortex-A9 processor-specific enhancements to deliver exceptional
performance and unmatched code density. The tools also support vectorizing compilation for the NEON media and signal processing
extensions, enabling developers to achieve product and project cost reductions through the elimination of separate DSPs. Cortex-A9
MPCore multicore processor debug including advanced cross triggering will be supported by the RealView ICE and Trace products.
The Cortex-A9 processor will also be supported by a range of hardware development boards supporting system prototyping in
FPGA and software development.
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