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ARM966E-S

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Embedded Core with Flexible Memory System & DSP Instruction Set Extensions

The ARM966E-S macrocell is a fully synthesizable 32-bit RISC processor aimed specifically at embedded hard real-time applications. The core implements the ARMv5TE instruction set and features an enhanced 16 x 32-bit multiplier capable of single cycle MAC operations, and 16-bit fixed point DSP instructions to accelerate signal processing algorithms and applications. The ARM966E-S processor has separate directly connected instruction and data tightly coupled memory (TCM), which have flexible sizes and run at the processor clock speed. The ARM966E-S processor supports ARM's real-time trace technology with the optional ETM9 Embedded Trace Macrocell. The ARM966E-S features a simple memory map providing an area and power efficient solution for applications which do not require complex memory management support. The core includes an AMBA AHBTM interface, and a coprocessor interface for connection to application acceleration hardware such as the VFP9-S floating point coprocessor.

 ARM966E-S Pic 

View larger image

Applications:

  • Mass storage devices
    • Hard disc drives, DVD drives
  • Networking systems
  • Automotive control
    • Powertrain with VFP9-S coprocessor
  • Wireless devices
  • Digital still cameras

Features:

  • 32/16-bit RISC architecture (ARMv5TE)
  • 32-bit ARM instruction set for maximum performance and flexibility
  • 16-bit Thumb instruction set for increased code density
  • Tightly Coupled Memories (TCMs)
  • EmbeddedICE-RT logic for real-time debug
  • Floating point capability with VFP9-S coprocessor
  • ETM interface for Real-time trace capability with ETM9
  • ARM-Synopsys Reference Methodology compliant deliverables
  • Optional MOVE coprocessor delivers video encoding performance

Benefits:

  • Single chip MCU and DSP solution
  • Deterministic performance from TCM memories
  • Simple single-processor software structure
    • No need for software partitioning across MCUs
    • Eliminates multi-MCU debugging
  • Single development toolkit:
    • Reduced development costs and shorter development cycle time
  • Optimized for hard real-time applications
  • Multiple sourcing from industry-leading silicon vendors
  • Code-compatible upward migration path to ARM10E family
  • Excellent debug support for SoC designers
  • Instruction set can be extended by the use of coprocessors
  • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.
 

 

 

Performance Characteristics Top Right Corner
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*0.180.1390 nm
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*  Speed
Opt		Speed
Opt		Speed
Opt		Area
Opt
*      
*Standard Cells --Advantage-HSMetro
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*
*      
*
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*Frequency* (MHz) 200250470250
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*Area (mm²) 210.380.35
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*Power † (mW/MHz) 0.700.250.110.07
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Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs.

The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

* Worst case conditions  –   0.18µm process - 1.62V, 125C, slow silicon ;  0.13µm process - 1.08V, 125C, slow silicon ;  90nm process - 0.9V, 125C, slow silicon

† Typical case conditions– 0.18µm process–1.8V, 25C, typical silicon ;  0.13µm process - 1.2V, 25C, typical silicon ; 90nm process - 1V, 25C, typical silicon

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