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ARM1156T2(F)-S

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The ARM1156T2-S™ and ARM1156T2F-S™ macrocells are fully synthesizable processors extending the ARM11™ family of cores with the features and performance levels required by high performance, high reliability, and real-time embedded applications. The ARM1156T2-S and ARM1156T2F-S cores are based on the powerful and versatile ARMv6 instruction set architecture for high performance and real-time applications with the Thumb-2 enhancements for high code density and implement a nine stage integer pipeline incorporating best in class branch prediction technology to deliver the highest instruction throughput of any ARM11 class processor.

 ARM1156 Chip Diagram
View larger image
The cores incorporate two AMBATM 3.0 AXI 64-bit systems interfaces for high instruction and data throughput, augmented by an AMBA 3.0 AXI 32-bit I/O interface for effective access to local peripheral devices. The cores support the configuration of fault-tolerant memory technologies for on-chip caches and tightly coupled SRAM arrays enabling high reliability system-on-chip (SoC) solutions. The ARM1156T2F-S incorporates the ARM11 Vector Floating Point coprocessor enhancing the capabilities of the integer core with exceptional floating point capacity and throughput.

Applications:
  • Wireless communications
    • Mobile baseband and high end wireless data communications
  • Automotive control systems
    • Powertrain, drive-by-wire and chassis control applications
  • Mass storage devices
    • Hard disk drives, DVD drives and network storage applications
  • Imaging devices
    • Printer and digital camera applications
  • Networking systems
    • Cable modems and home gateway applications
  • Industrial control systems
    • Motion control applications

Features:

  • 32/16-bit architecture (ARMv6T2)
  • Thumb-2 16/32-bit instruction set for high performance high density code
  • DSP and SIMD extensions for media and filtering algorithms
  • Configurable instruction and data caches
  • Configurable tightly coupled instruction and data memory
  • Fault tolerant memory interfaces for on-chip RAM technologies
  • Global branch prediction unit
  • Configurable memory protection unit for application, data and stack bounding
  • 64-bit AMBA 3.0 AXI instruction and data interfaces
  • 32-bit AMBA 3.0 AXI local peripheral interface
  • High performance vector floating point unit (ARM1156T2F-S)
  • Vectored Interrupt Controller interface for low interrupt latency
  • CoreSight™ enhanced debug system compatible
  • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.

Benefits:

  • Efficient use of memory reduces system cost
  • Low power increases battery life for portable applications
  • Fast deterministic behaviour reduces over-engineered solutions
  • Configurability allows the core to be tailored to system requirements
  • Thumb-2 instruction set reduces memory and power costs
  • Fixed point DSP and SIMD instructions lessen the need for separate DSP sub-systems, thereby reducing system cost.
  • Enhanced reliability reduces field costs and increases safety
  • High performance system busses maximize system data throughput
  • CoreSight provides complete visibility inside SoCs thereby reducing time to market
  • Broad range of industry leading tools and software support for high quality software development
 

 

 

Performance Characteristics
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* 90 nm
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*     Speed
Opt		 Area
Opt
*        
* Standard Cells   Advantage-HS Metro
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* Memories   Advantage Metro
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*        
*
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* Frequency* (MHz)   620 320
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* Area with cache (mm²)   2.40 1.45
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* Area without cache (mm²)   1.75 0.85
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* Cache Size   16K/16K 16K/16K
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* Power with cache† (mW/MHz)   0.51 0.31
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* Power w/o cache† (mW/MHz)   0.42 0.24
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*

Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs.

The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

The cache sizes are specified as InstructionCache/DataCache. The area w/o cache numbers quoted exclude RAM area, but include all logic including memory management, cache control and debug. The area with cache numbers quoted includes the core, the specified instruction and data caches and all necessary RAMs.

* Worst case conditions –  0.13µm process - 1.08V, 125C, slow silicon ;  90nm process - 0.9V, 125C, slow silicon
† Typical case conditions – 0.13µm process - 1.2V, 25C, typical silicon ; 90nm process - 1V, 25C, typical silicon

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