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SecurCore SC100

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The SecurCore®  SC100TM processor provides the lowest cost introduction to 32-bit ARM secure technology, and enables existing 8 and 16-bit smart card products to migrate to the 32-bit ARM platform easily.

The SC100 processor is based on the ARM7 processor family, the world’s most successful 32-bit processor. More than 5 billion devices based on ARM7 have been shipped worldwide. The SC100 processor supports both ARM and Thumb® instruction sets. The Thumb instruction set provides significantly better code density than existing 8 and 16-bit cores. A very wide range of software development tools are available from various vendors.

The SC100 processor has a small 35K gate implementation and is available through a dedicated Foundry Program, further lowering the cost of entry.

 

  ARM SC100

Security Features

Each SecurCore product incorporates the following security features:

  • Randomized processor layout based on customer design specifications, resists probing.
  • Specific counter-measures to help prevent analysis of current flows and other forms of attack
  • Soft core methodology to allow maximum flexibility and resistance to probing
  • Secure one-way development process
  • Controlled access to design stages via flexible software and emulation solutions
  • Secure low-cost Memory Protection Unit (MPU)
  • Full support for integration of vendor-specific security features
  • Advanced, secure debugging and test methodology
  • Removable production debug for increased security

Other Key Features

In addition, each product incorporates a subset of the following key features:

  • Fully synthesizable design for easy implementation
  • Wide tools support - Full support from RealView® Microcontroller Development Kit (the Keil uVision environment), the most popular smart card development tool chain in the industry
  • Connect to standard fabric IP - AMBA® interconnect compatibility for fast and efficient system design with peripherals and memories

Benefits

  • Application of 32-bit processing through a compact synthesizable processor
  • Higher system performance
  • Faster time to market
  • Wide range of software development tools available
  • Reduced development costs
  • Multiple sourcing from industry-leading silicon vendors
  • Excellent debug support for SoC designers
 

 

 

Performance Characteristics
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*0.13
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*  Area
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*Frequency* (MHz) 80
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*Area (mm²) 0.25
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*DMIPS/MHz 0.79
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*DMIPS/mW 6.6
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*Gate Count 35K
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*Power † (mW/MHz) 0.12
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Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM standard cell libraries and RAMs.

The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

* Worst case conditions –   0.18µm process - 1.62V, 125C, slow silicon ;  0.13µm process - 1.08V, 125C, slow silicon
† Typical case conditions– 0.18µm process–1.8V, 25C, typical silicon ;  0.13µm process - 1.2V, 25C, typical silicon

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