The Arm CoreLink DMC-620 Dynamic Memory Controller
The Arm CoreLink DMC-620 Dynamic Memory Controller is designed to provide an optimal memory access solution for SoCs deployed in infrastructure applications such as servers, High-Performance Computing (HPC), and networking.
The CoreLink DMC-620 offers support for sophisticated RAS features such as end-to-end data parity protection, corrected data write-back, retry on uncorrectable ECC errors, memory scrubbing, and standardized error reporting.
Low memory latency with high bandwidth use, the CoreLink DMC-620 delivers QoS and high performance for data transfers from SoC to high-density DRAM memory.
CoreLink DMC-620 provides integrated Arm TrustZone Address Space Control (ATASC) with programmable memory access protection. It also supports multiple DRAM standards, addressing up to 1TB of DRAM memory so designers can scale the DRAM footprint of high-end systems.
CoreLink DMC-620 is built on top of a family of silicon-proven DMC products that guarantee interoperability with any DFI-compliant DDR PHY and with JEDEC-compliant DDR4, DDR3, and DDR3L DRAM memory. Deploying CoreLink DMC-620 in your SoC delivers cost savings and helps to accelerate your tape-out.
Arm has extensive experience optimizing, tuning and validating performance and interoperability for subsystems. Talk to an Arm expert about the right silicon-proven DMC for you.
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