Comprehensive Component Library for Debug and Trace Functionality
The CoreSight SoC-400 library offers configurable components, including debug access, trace generation manipulation and output, cross triggering, and time stamping to meet the exact requirements of your system, regardless of size. With a rich development history, CoreSight SoC-400 is the standard for Arm-based SoC designs and can help safeguard against costly delays. Widely accepted as the standard for debug and trace IP, it enjoys broad support from the tooling ecosystem.
Features and Benefits
Enables you to build the interface between an external debugger, using, JTAG or SWD for example, and processors, memory systems, and other CoreSight components. Post-mortem debugging reduces both bug cost and the time to market.
Trace lets you generate and end trace buses, and provides the links between source and sink. Arm provides separate trace components for the generation of system trace, the System Trace Macrocell (STM), and the management of intermediate and termination of trace buses, Trace Memory Controller (TMC).
Hardware and software co-development with a debugger in simulation and emulation helps improve reliability.
Components can control actions from and to other components.
Faster bring up means a reduced time to market.
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