On-Chip Visibility for Fast Bug Diagnosis and Performance Analysis
The Arm CoreSight Trace Memory Controller (TMC) is a configurable trace component to terminate trace buses into buffers, FIFOs, or alternatively, to route trace data over AXI to memory or off-chip to interface controllers.
Enables trace to be stored in a dedicated SRAM, used either as a circular buffer or as a FIFO. The functionality of this configuration is a superset of the functionality of the ETB configuration.
Enables trace to be routed over an AXI bus to system memory or to any other AXI slave.
Enables trace to be stored in a dedicated SRAM, used as a circular buffer. This configuration is similar to the CoreSight ETB.
Fine tuning chip performance requires optimum visibility. Find out how CoreSight TMC can help your designers achieve optimum performance.
CoreSight ELA-500 Embedded Logic Analyzer
An effective way to observe low-level signals, by offering a way to zoom into the root cause of data corruption.
Arm processors include the ultra-low power Cortex-M series, real-time response Cortex-R series, and the server-class Cortex-A series.
Graphics and Multimedia
Arm Mali media IP offer high-performing, energy-efficient media processing across a large and growing number of mobile and consumer devices, including smartphones, tablets, TVs and wearables.
The Arm family of Dynamic Memory Controllers manage the differing demands of multiple processing elements while delivering maximum DRAM bandwidth.
Arm Development Studio
An end-to-end software development environment for all Arm-based systems, including Arm Compiler, debuggers, IDEs, performance analysis tools, models and middleware.
CoreSight TMC Resources
Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.
- Technical Reference Manual
- CoreSight Technical Introduction
- Introduction to CoreSight SoC-400
- Key steps to create a debug and trace solution for an Arm SoC
- CoreSight SoC enabling efficient design of custom debug and trace subsystems for complex SoCs
- Better Trace for better software with CoreSight STM
- Low Pin-count Debug Interfaces for Multi-device Systems
- Taking the fear out of silicon debug
- Video interview with CoreSight tech lead Mark LaVine