High-Performance Cache Controller
The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, including the Cortex-A5, Cortex-R4, Cortex-R5, Arm11MPCore, Arm1176, Arm1156, and the Mali-200 graphics processor.
Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip.
Memory access on-chip typically uses much less power compared to going off-chip, and free up bandwidth.
CoreLink level 2 cache controllers are designed to match processor requirements and easily integrate into AMBA AXI or AHB interconnects.
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Arm processors include the ultra-low power Cortex-M series, real-time response Cortex-R series, and the server-class Cortex-A series.
Graphics and Multimedia
Arm Mali media IP offer high-performing, energy-efficient media processing across a large and growing number of mobile and consumer devices, including smartphones, tablets, TVs and wearables.
The Arm family of Dynamic Memory Controllers manage the differing demands of multiple processing elements while delivering maximum DRAM bandwidth.
Arm CoreLink Interconnect provides the components and the methodology to build SoCs based on the latest AMBA specifications, maximizing the efficiency of data movement and storage, and delivering the required performance.
CoreSight Debug and Trace
Arm CoreSight technology is a set of tools that can be used to debug and trace software that runs on Arm-based SoCs.
Arm Socrates significantly reduces the time to select, configure and create Arm IP that is error free and ready for SoC integration.