The Arm CoreLink CCI-400 Cache Coherent Interconnect
The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB.
Features and Benefits
Widely licensed since 2011, the CoreLink CCI-400 is mature, silicon proven, and has shipped in millions of devices.
The CoreLink CCI-400 supports smaller 2-cluster, 1 or 2 memory interfaces, and is the smallest cache coherent interconnects available from Arm.
Part of a complete suite of system IP from Arm designed, tested, and optimized with the latest Arm technology, including the Cortex and Mali processor series, and CoreLink system IP.
Where Innovation and Ideas Come to Life
Arm technology is used in various applications throughout the car including Advanced driver-Assistance Systems (ADAS) and autonomous driving.
Talk with an Expert
A trusted interconnect solution must work for multiple applications and result in an improved user experience. Talk to an Arm expert about the highest efficiency coherent interconnect to do the job.
Explore More Options and Features
Arm processors include the ultra-low power Cortex-M series, real-time response Cortex-R series, and the server-class Cortex-A series.
Graphics and Multimedia
Arm Mali media IP offer high-performing, energy-efficient media processing across a large and growing number of mobile and consumer devices, including smartphones, tablets, TVs and wearables.
CoreSight Debug and Trace
Arm CoreSight technology is a set of tools that can be used to debug and trace software that runs on Arm-based SoCs.
The Arm family of Dynamic Memory Controllers manage the differing demands of multiple processing elements while delivering maximum DRAM bandwidth.
System Memory Management Units
A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization.
Arm generic interrupt controllers (GIC) perform critical tasks of interrupt management, prioritization and routing.