Full coherency for up to 12 processor clusters (48 cores), and support for 1 MB to 32 MB of L3 system cache for high compute density.
Full coherency for up to 8 processor clusters (32 cores), and support for 1 MB to 32 MB of L3 system cache for high-performance compute and IO.
Full coherency for up to 4 processor clusters (16 cores), and support for 1 MB to 16 MB of L3 system cache for high-performing 16-core systems.
Full coherency for up to 4 processor clusters (16 cores), and support for 0 MB to 8 MB of optional L3 system cache for small footprint, cost-sensitive applications.
Cortex Processors
Arm processors range from ultra-low power Cortex-M series to server-class Cortex-A series.
CoreSight Debug and Trace
Arm CoreSight technology is a set of tools that can be used to debug and trace software that runs on Arm-based SoCs.
Memory Controllers
The Arm family of Dynamic Memory Controllers manage the differing demands of multiple processing elements while delivering maximum DRAM bandwidth.
System Memory Management Units
A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization.
Interrupt Controllers
Arm generic interrupt controllers (GIC) perform critical tasks of interrupt management, prioritization and routing.
