Interconnects Optimized for Any Size Application
The Arm CoreLink CCN family scales across the performance spectrum for all kinds of networking, storage and server applications. It supports from 1 to 48 cores along with an integrated, configurable Level 3 system cache. The L3 system cache allows IO and accelerators to allocate memory on chip, offering reduced latency and power by minimizing accesses to external memory.
The CoreLink CCN family supports the latest Arm 64-bit processors and AMBA 5 CHI (Coherent Hub Interface) protocol targeting networking infrastructure and server applications.
The CoreLink CCN family includes an optional integrated level 3 (L3) system cache and snoop filter functions. The L3 cache offers low latency on-chip system cache. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.
The CoreLink CCN family is optimized to work with the CoreLink DMC-520 Dynamic Memory Controller providing a high-bandwidth interface for off-chip memory, such as DDR3, DDR3L and DDR4 DRAM.
Full coherency for up to 12 processor clusters (48 cores), and support for 1 MB to 32 MB of L3 system cache for high compute density.
Full coherency for up to 8 processor clusters (32 cores), and support for 1 MB to 32 MB of L3 system cache for high-performance compute and IO.
Full coherency for up to 4 processor clusters (16 cores), and support for 1 MB to 16 MB of L3 system cache for high-performing 16-core systems.
Full coherency for up to 4 processor clusters (16 cores), and support for 0 MB to 8 MB of optional L3 system cache for small footprint, cost-sensitive applications.
Still unsure which CoreLink CCN product is right for your SoC project? Talk to an Arm expert and learn more.
Arm processors range from ultra-low power Cortex-M series to server-class Cortex-A series.
CoreSight Debug and Trace
Arm CoreSight technology is a set of tools that can be used to debug and trace software that runs on Arm-based SoCs.
The Arm family of Dynamic Memory Controllers manage the differing demands of multiple processing elements while delivering maximum DRAM bandwidth.
System Memory Management Units
A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization.
Arm generic interrupt controllers (GIC) perform critical tasks of interrupt management, prioritization and routing.
CoreLink Cache Coherent Network Family Resources
Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.