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CoreSight 片上跟踪和调试体系结构

CoreSight SoC Components Image (View Larger CoreSight SoC Components Image) The CoreSight™ architecture documents consist of a set of architecture specifications, defining ARM debug & trace architecture. These specifications are:
  • ARM Debug Interface (ADI) architecture
  • ARM processors real-time trace macrocells (ETM & PTM) architecture
  • ARM CoreSight component architecture 
  • High Speed Serial Trace Port

 

Embedded Trace Macrocell™ Architecture Specification

An Embedded Trace Macrocell (ETM) is a real-time trace module providing instruction and data tracing of a processor. An ETM is an integral part of an ARM CoreSight debug and real-time trace solution.

This specification describes the ARM Embedded Trace Macrocell (ETM) architecture. All ETMs conform to a version of this architecture that covers the following areas of functionality:

  • The Programmer’s Model
  • The Trace Port Protocol
  • The Physical Interface

Embedded Trace Macrocell™ Architecture Specification

CoreSight Program Flow Trace™ Architecture Specification

A Program Trace Macrocell (PTM) is a real-time trace module providing instruction tracing of a processor. A PTM is an integral part of an ARM CoreSight debug and real-time trace solution.

This specification describes the Program Flow Trace Macrocell ™ (PTM) architecture. All PTMs conform to a version of this architecture that covers the following areas of functionality:

  • The Programmer’s Model
  • The Trace Port Protocol
  • The Physical Interface

CoreSight™ Program Flow Trace™ Architecture Specification

CoreSight Architecture Specification

The CoreSight architecture provides a set of standard interfaces and programmer model views enabling partners to define CoreSight components and integrate them within the CoreSight infrastructure.

CoreSight™ Architecture Specification




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