CoreLink™ Dynamic Memory Controllers (DMC) are designed for efficient operation with ARM CPUs, media processors and systems IP. They provide highly optimized arbitration and scheduling algorithms to maximize use of the available DRAM bandwidth. At the same time, they manage the latency requirements of the initiators through Quality of Service Why choose a CoreLink Dynamic Memory Controller?
The interface to dynamic memory is one of the key control points in a SoC that can critically affect system performance. To ensure that the interface efficient implementation, it is important to choose a solution that has been carefully designed to work with both the on-chip AMBA interconnect and the off-chip DRAM memory protocol.
ARM has a long history of designing memory controllers for AMBA-based systems. Working closely with the CPU and media processor teams and ARM's network of Partners, the current product offerings represent the 3rd generation of controllers.
The DMC-34X and PL24X families of controllers have been developed to provide the optimal compatibility with the network interconnect solutions to enable the performance demanded by Cortex-A, Cortex-R and Mali processors.
Verification and Benchmarking
Understanding the performance and functionality of the memory controller in a system context is critical to the specification and development of the controller. The system level verification and benchmarking performance ensures the delivery products that have been fully qualified alongside the cores and on-chip interconnect. These results then drive the specifications of both current and future memory controllers. They ensure our Partners have the efficient, low-risk, easy to integrated solutions that enable development to proceed smoothly meeting performance goals and delivering time to market.
