Efficient movement of data across the chip
Massive growth in system integration places on-chip communication and interconnect at the center of system performance. Traffic interactions have become complex and, if left unchecked can cause poor, unpredictable system performance. The ARM® CoreLink™ interconnect family from the home of AMBA® is the lowest risk solution for on-chip communication. Designed and tested with ARM Cortex and Mali processors, CoreLink interconnect from ARM provides balanced service for both low latency and high bandwidth data streams.
The interconnect improves system performance and reduces power
ARM CoreLink Interconnect provide the components and the methodology for designers to build SoCs based on the AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost.
There are three families of interconnect products:
- CoreLink CCN Cache Coherent Network - Designed for infrastructure applications.
- CoreLink CCI Cache Coherent Interconnect - Optimized for mobile.
- CoreLink NIC Network Interconnect - Highly configurable for SoC wide connectivity, multiple applications.
Highest Performance Interconnect
The CoreLink CCN cache coherent network family targets infrastructure applications, optimized for ARM Cortex processors, supporting the latest ARMv8-A processors including the high performance Cortex-A72 and high efficiency Cortex-A53. They offer scaling from 1 to 48 cores and an integrated configurable L3 cache. The CCN family is scalable across multiple infrastructure applications and provides the system throughput required from high performance systems. The L3 can act as a system cache allowing IO and accelerators to allocate cache memory on chip, offering reduced latency and power by reducing accesses to external memory. The CCN family are optimised for AMBA 5 CHI processors and memory controllers, and AMBA 4 ACE-Lite/AXI4 for IO.
Highest Efficiency Interconnect
The CoreLink CCI cache coherent interconnect family provide full coherency between the L2 caches of multicore processors including Cortex-A53 and Cortex-A57, and I/O coherency with other masters such as the Mali GPU, sharing data in L2 caches of the processors. For mobile applications hardware managed cache coherency is a fundamental technology for big.LITTLE processing, allowing the operating system to choose the right processor for the right job.
- CoreLink CCI Cache Coherent Interconnect offers the smallest and lowest power multi-cluster interconnect:
- CoreLink CCI-550 Cache Coherent Interconnect for best in class performance with ARMv8-A processors with improvements in efficiency, performance and scalability
- CoreLink CCI-500 Cache Coherent Interconnect for coherency with up to four clusters including big.LITTLE and coherent accelerators, and higher performance and efficiency with integrated snoop filter
- CoreLink CCI-400 Cache Coherent Interconnect for coherency with up to two clusters (8 cores), essential for big.LITTLE, also applicable to low-cost infrastructure
Highly Configurable Interconnect
The CoreLink NIC network interconnect family offers a low-power, low latency rest of SoC interconnect. It can be tailored to suit your system requirements, and are widely licensed across many applications, from Cortex-M based microcontrollers to Cortex-A based powerful SoCs. It is a fully configurable, hierarchical connectivity for AMBA that can be optimized using the latest ARM IP Tooling.
Introduction to AMBA 4 ACE and big.LITTLE Processing Technology
This paper focuses on the AMBA® ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, distributed virtual memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE™ software to run effectively, increasing system efficiency.
Quality of Service in ARM Systems: An Overview
Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in ARM® systems.
QoS for High-Performance and Power-Efficient HD Multimedia
Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.
Introduction to QoS Virtual Networks (QVN)
This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.