Interconnect improves system performance and reduces power
Massive growth in system integration places on-chip communication and interconnect at the centre of system performance. Traffic interactions have become complex and, if left unchecked can cause poor, unpredictable system performance.
The CoreLink Interconnect family from the home of AMBA is the lowest risk solution for on-chip communication. Designed and tested with ARM Cortex and Mali processors, CoreLink interconnect from ARM provides balanced service for both low latency and high bandwidth data streams.
The CoreLink Interconnect family includes the following products for AMBA protocols:
- CoreLink CCI-400 Cache Coherent Interconnect for AMBA 4 CPU clusters and I/O coherency
- CoreLink NIC-400 Network Interconnect fully configurable for AMBA 3 and long bursts with AMBA 4
- Network Interconnect (NIC-301) for AMBA 3 systems including support for AXI, AHB and APB
- Advanced Quality of Service (QoS-301) option for NIC-301
- AMBA Design Kit (ADK) for AMBA 2 systems including AHB and APB
Cache Coherency across clusters of CPU, GPU and accelerators
The CoreLink CCI-400 provides full coherency between the L2 caches of two multicore Cortex-A15 processors and I/O coherency with up to three other master, such as the Mali GPU, sharing data in either of the L2 caches of the Cortex-A15 processors. The CCI-400 routes traffic to up to three slaves (e.g. two high performance channels to the memory controler and one to the rest of the system) using virtual channels to prevent blocking and barriers to preserve ordering.
Network features in CoreLink Network Interconnect (NIC-400, NIC-301)
The CoreLink interconnect family delivers key technologies commonly associated with network-on-chip products:
- Predictability of physical implementation
- Communication control for system performance optimization
- Communication visibility for software optimization
- Reliable integration of complex system containing third party IP core
The CoreLink NIC-400 comes with options for QoS traffic regulation (QoS-400), virtual channels to prevent blocking (QVN-400) and thin links to reduce wiring (TLX-400). The NIC-400 supports long bursts in AXI4 for higher efficiency streaming media and hierarchical clock gating to dramtically reduce idle power.
Increasing performance with AMBA 3 AXI
The majority of high performance ARM designs now use the AMBA 3 AXI standard, especially for the high performance low latency connection from processor to dynamic memory controller.Technical features of the high-performance AMBA 3 AXI protocol include:
- Uni-directional channel architecture. Information flow is in one direction only, enabling very simple bridging between clock domains. This reduces the gate count and hence timing penalty when signals traverse complex SoCs.
- Support for multiple outstanding transactions. This enables parallel execution of bursts, resulting in greater data throughput. This facilitates both high performance when required, and low power as tasks complete in a shorter time.
- Independent Address and Data channels. This enables per-channel optimization, by breaking timing paths as required to maximize clock frequency and minimize latency.
- Increased flexibility. With symmetrical Master and Slave interfaces, AXI technology can be easily used for anything from point-point to multi-hierarchy systems.
Ease of interconnect design speeds time to market
The CoreLink Interconnect family gives SoC architects the fastest time to market for products that deliver unparalleled internet multi-media experience.


The CoreLink™ Interconnect Family provides on-chip AMBA connectivity for components implementing any combination of AMBA® AXI™, 







