CoreLink Interconnect - AMBA on-chip connectivity

Interconnect improves system performance and reduces power

Massive growth in system integration places on-chip communication and interconnect at the center of system performance. Traffic interactions have become complex and, if left unchecked can cause poor, unpredictable system performance.

The CoreLink Interconnect family from the home of AMBA is the lowest risk solution for on-chip communication. Designed and tested with ARM Cortex and Mali processors, CoreLink interconnect from ARM provides balanced service for both low latency and high bandwidth data streams.

The CoreLink Interconnect family includes the following products for AMBA protocols:

• CoreLink CCN-504 Cache Coherent Network for AMBA 5 CPU clusters, up to 16 cores and L3 cache
• CoreLink CCI-400 Cache Coherent Interconnect for coherency with up to 8 cores, essential for big.LITTLE
• CoreLink NIC-400 Network Interconnect fully configurable for AMBA 4 and AMBA 3 including AXI, AHB and APB
• Network Interconnect (NIC-301) for AMBA 3 systems including support for AXI, AHB and APB
• Advanced Quality of Service (QoS-301) option for NIC-301
• AMBA Design Kit (ADK) for AMBA 2 systems including AHB and APB

Cache Coherency across clusters of CPU, GPU and accelerators

The CoreLink CCN-504 and CCI-400 interconnects provide full coherency between the L2 caches of multicore  processors including Cortex-A15, Cortex-A53, Cortex-A57, and I/O coherency with other masters such as the Mali GPU, sharing data in L2 caches of the processors. 

Hardware managed cache coherent is a fundamental technology for big.LITTLE processing, allowing the operating system to chose the right processor for the right job.

For enterprise applications CCN-504 offers scaling up to 16 processors cores and integrates a shared level 3 (L3) cache. This L3 allows IO and accelerators to allocate cache memory on chip, offering reduced latency and power by reducing accesses to external memory.

Network features in CoreLink Network Interconnect (NIC-400, NIC-301)

The CoreLink interconnect family delivers key technologies commonly associated with network-on-chip products:

• Abilty to distribute swithing and routing functions between many and complex IP blocks
• Predictability of physical implementation
• Communication control for system performance optimization
• Communication visibility for software optimization
• Reliable integration of complex system containing third party IP core

The CoreLink NIC-400 comes with options for QoS traffic regulation (QoS-400), virtual networks to prevent blocking (QVN-400) and thin links to reduce wiring (TLX-400). The NIC-400 supports long bursts in AXI4 for higher efficiency streaming media and hierarchical clock gating to dramatically reduce idle power.

Increasing performance with AMBA AXI3™ and AXI4™

Technical features of the high-performance AMBA AXI3 and AXI4 protocols include:

• Uni-directional channel architecture. Information flow is in one direction only, enabling very simple bridging between clock domains. This reduces the gate count and hence timing penalty when signals traverse complex SoCs
• Support for multiple outstanding transactions. This enables parallel execution of bursts, resulting in greater data throughput. This facilitates both high performance when required, and low power as tasks complete in a shorter time
• Independent Address and Data channels. This enables per-channel optimization, by breaking timing paths as required to maximize clock frequency and minimize latency
• Increased flexibility. With symmetrical Master and Slave interfaces, AXI technology is easily used for anything from point-point to multi-hierarchy systems

Ease of  interconnect design speeds time to market

The CoreLink Interconnect family gives SoC architects the fastest time to market for products that deliver unparalleled internet multi-media experience.