Gives System Visibility to All Developers
With the increasing complexity of modern SoCs, access to the most comprehensive suite of debug and trace solutions is critical to reduce time-to-market and validation effort.
The ARM® CoreSight™ family of IP products offer solutions to address the needs of silicon partners and developers alike, from SoC bring up to software debug and system optimization and finally post-mortem debug.
Original Equipment Manufacturers (OEMs) are expecting silicon providers to provide a reliable and complete hardware and software system ready for applications development, and this is a key differentiator. A well thought-out debug and trace solution helps partners address these challenges.
CoreSight offerings include components for the implementation solutions for debug access, instruction tracing, cross-triggering and time-stamping.
CoreSight SoC-400 is the comprehensive set of debug and trace IP that enables SoC designers to build a bespoke solution to optimize their system.
Embedded Logic Analyzer
CoreSight ELA-500, Embedded Logic Analyzer, ensures the fastest silicon debug by providing low level signal visibility into ARM IP and 3rd party IP.
System Trace Macrocell
CoreSight STM-500, System Trace Macrocell, gives real-time SoC level visibility at affordable cost up to end product.
Trace Memory Controller
CoreSight TMC-500, Trace Memory Controller, enables real-time trace to be used cost effectively during all the product development phases, giving real-time visibility to all developers including third party software developers.
Introduction to ARM CoreSight SoC-400
ARM CoreSight debug and trace technology offers a comprehensive solution for the entire SoC. CoreSight SoC-400 is a kit of parts that enables software developers and SoC designers to develop high-performance systems while decreasing development time and risks.
The industry name for debug and trace
CoreSight technology is licensed by all major silicon providers, specified by leading OEMs across markets and used by hundreds of thousands of software engineers to develop, debug, optimize and maintain in the field ARM processor-based products.
Higher productivity and lower risk development
Using CoreSight trace macrocells (e.g ETM), software and hardware developers can identify real-time software or hardware defects and quickly resolve them, ensuring higher productivity and lower risk developments.
Universal tool support
CoreSight debug and trace is supported by ARM DS-5 Development Studio and more than 25 tools vendors worldwide and locally.
Higher quality products
CoreSight technology provides mission critical on-chip visibility to industry developments tools enabling embedded software, system and hardware engineers to develop higher quality and performance software and platforms.
A scalable, cost effective debug and trace SoC solution
An open architecture
The CoreSight architecture is an open architecture, enabling Partners to leverage the ARM solution and plug-in their own debug and trace components.
Faster bring up means a reduced time-to-market
Hardware/Software co-development via debugger in simulation and emulation
Performance optimization (both hardware and software)
Reduced bug cost
Reduced time to market
Key steps to create a debug and trace solution for an ARM SoC
The global cost of debugging software has risen to $312 billion annually. A new whitepaper: "CoreSight SoC enabling efficient design of custom debug and trace subsystems for complex SoCs", outlines the key steps to create a debug and trace solution for an ARM SoC.
Technical Introduction to ARM CoreSight
ARM® CoreSight™ technology is the industry name for debug and trace. This document introduces the concepts which will help you to get the most out of CoreSight. You will learn:
- Elements of a CoreSight design
- Processor trace architectures
- Debug access and DAP topology
- Typical CoreSight systems
Better trace for better software with ARM CoreSight
This white paper explores the limitations of existing software debug and trace technologies, and explains how the ARM® CoreSight™ System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, whilst leveraging existing open source trace infrastructures.
Low Pin-count Debug Interfaces for Multi-device Systems
This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, whilst maintaining support for multi-core systems and interoperability with test.