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CoreSight SoC Components

CoreSight SoC Components Image (View Larger CoreSight SoC Components Image)
The CoreSight™ SoC components in conjunction with the CoreSight Trace macrocells provide all the infrastructure required to debug, monitor, and optimize the performance of a complete System on Chip (SoC) design.   

They address the requirement for a multi-core debug and trace solution with high bandwidth for whole systems beyond the core.

CoreSight SoC components and CPU specific Integration Kits are delivered as part of the CoreSight Design Kits available for each CPU (CDK-A9, CDK-A8, CDK-A5, CDK-R4, CDK-11, CDK-9).

CoreSight SoC-400 provides configurable versions of all of the CoreSight SoC components with AMBA Designer support for graphical system design and automated IP stitching.

 


The CoreSight SoC components provide the following capabilities for system-wide trace:

  • Debug and trace visibility of whole systems
  • Cross triggering support between SoC subsystems
  • Multi-source trace in a single stream
  • Standard programmer's models for standard tools support
  • Open interfaces for third party cores
  • Low pin count
  • Low silicon overhead

This enables

  • Higher visibility of complete system operation through fewer pins 
  • Standard solution across all silicon vendors for widest tools support
  • Re-usable for single ARM processor, multi-core or processor and DSP systems
  • Faster time-to-market for more reliable and higher performance products
  • Support of highest frequency processor

CoreSight Debug Performance

The CoreSight Debug Access Port is a high performance debug access port enabling external debuggers to access cores and internal system buses such as memory buses. The DAP provides a combined debug port supporting traditional JTAG and a high performance 2 pin debug interface (Serial Wire Debug).

DAP mode  

Number of pins   

Typical frequency  

Serial Wire Debug

 2

 > 50 MHz

 JTAG

 4-6

 50 MHz

CoreSight SoC Components, Trace Port & ETB Size

The CoreSight SoC components provide a complete SoC level debug & trace solution with low silicon and low pin count overheard. The architecture of all CoreSight SoC components support modern SoC designs such as multi power & clock domain and secure SoCs. Main performance characteristics of the CoreSight SoC components are:

 

Characteristics 

Performance 

Operating frequency

400MHz on 65nm LP (typical)
250MHz on 90nm
Support for multi clock and power domains  

 Gate Count
NAND2.1 equivalent

 ~ 40 Kgates for a full debug and multicore tracing (TPIU + ETB)


What are CoreSight SoC components?

CoreSight SoC components are all the components except for the Trace Memory Controller (TMC) and CoreSight trace macrocells, available from ARM for debug and real-time trace of single or multicore platforms.

CoreSight SoC components fit into the following categories:

  • CoreSight Buses
  • CoreSight Control and Access Components
  • Trace Links
  • Trace Sinks

CoreSight Buses

The CoreSight systems use the following bus protocols to connect components together, and to enable integration in a SoC:

Bus Type Overview

AMBA Advanced Trace Bus (ATB) 

The ATB transfers trace data through CoreSight infrastructure in a SoC. Trace sources are ATB masters, and sinks are ATB slaves. Link components provide both master and slave interfaces

AMBA 3 Advanced Peripheral Bus
(AMBA 3 APB)

The Debug APB is a bus provided non-invasive, on-the-fly configuration of debug and trace components in a CoreSight compliant SoC.

Advanced High-performance Bus (AHB)

CoreSight supports access to a system bus infrastructure using the AHB Access Port (AHB-AP) in the DAP. The AHB-AP provides an AHB master port for direct access to system memory

CoreSight Control and Access Components

Control and access components configure, provide access to, and control debug logic and the generation of trace. They do not generate trace, or process the trace data.

The CoreSight control and access components are:

Component Overview

Debug Access Port (DAP)

The DAP provides real-time access by the debugger software to the JTAG scan chains in the chip, to the AMBA bus system and to all debug and trace configuration registers. For multicore systems, debug access is maintained, even if one core is powered down or asleep.
The DAP implements a dual debug port with support of 2 pin debug Serial Wire Debug and JTAG

Embedded Cross Trigger (ECT)

The ECT is a modular component that supports the interaction and synchronization of multiple triggering events within a SoC. 

Multi Processors Trace and Trace Links

Links provide connection, triggering, and flow of traced data

Component Overview

Trace Funnel

The Trace Funnel combines up to eight trace sources on a single funnel. A static arbitration scheme selects the input trace stream to pass at any instant. The static arbitration permits reorganization of the slave port priorities between trace sessions. Chaining of funnels together is possible, with the ATB output from one funnel connected to an ATB input port of another.This enables both the number of inputs to be increased and independent systems to be connected. 

Replicator 

The Replicator enables wiring together of two trace sinks and operated on the same incoming trace stream. The input trace stream is output on two ATB ports that can then operate independently. 

Synchronous 1:1 ATB Bridge 

The Synchronous ATB Bridge provides a register slice that enables timing closure through the addition of a pipeline stage 

Collecting Trace and Trace Sinks

Sinks are the endpoints for trace data on the SoC.

Sink Overview

Trace Port Interface Unit (TPIU)

The TPIU is an ATB slave that drains trace data off the chip.It acts as a bridge between the on-chip trace data and a data stream, captured by a Trace Port Analyzer. (TPA)                                                                                                                                                                       The Formatter within the TPIU combines the source data and IDs into a single data stream, to enable serialization of data, inserting trigger packets on trigger detection. 

Embedded Trace Buffer (ETB)

The Embedded Trace Buffer (ETB) is an ATB slave and provides on-chip storage of trace data using a configurable sized RAM. 
The Formatter in the ETB combines the source data and IDs into a single data stream. The Formatter operates in an identical manner to the Formatter in the TPIU.

Serial Wire Output (SWO)   

SWO is a trace sink similar to the TPIU. It can only trace one source, the ITM. It outputs the data stream off chip through a single-pin interface 

Trace Port Interface Unit Lite 

The Trace Port Interface Unit Lite (TPIU-Lite) is a reduced feature, low gate count version of the TPIU; in particular it is able to operate with only one trace source. 


CoreSight Design Kits

CoreSight SoC components are available as part of the CoreSight Design Kit products (and not available stand alone).

 Related Products

 CoreSight Products

Benefits

ARM926EJ-SARM946E-S,  ARM966E-S,  ARM968E-S

CoreSight Design Kit for ARM9E (CDK-9)

Complete debug and real-time trace solution for ARM9E processors.

ARM1136J(F)-SARM1156T2(F)-SARM1176JZ(F)-SARM11 MPCore

CoreSight Design Kit for ARM11  (CDK-11)

Complete debug and real-time trace solution for ARM11 processors.

 Cortex-R4

CoreSight Design Kit for Cortex-R4 (CDK-R4)

Complete debug and real-time trace solution for Cortex-R4 processors.

 Cortex-A5

CoreSight Design Kit for Cortex-A5 (CDK-A5)

Complete debug and real-time trace solution for Cortex-A5 processors.

 Cortex-A8

CoreSight Design Kit for Cortex-A8 (CDK-A8)

Complete debug and real-time trace solution for Cortex-A8 processors.

 Cortex-A9

CoreSight Design Kit for Cortex-A9 (CDK-A9)

Complete debug and real-time trace solution for Cortex-A9 processors.

CoreSight Tools Support

CoreSight SoC components are supported by over 20 tool vendors. For more details on tool vendors supporting CoreSight components click here and look on the 'Tools Support' tab


Serial Wire Debug Whitepaper

An overview of ARM Serial Wire Debug 2 pin debug technology  (245KB)

 

 

 
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