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CoreSight Infrastructure

CoreSight SoC Components Image (View Larger CoreSight SoC Components Image) The CoreSight™ Infrastructure in conjunction with the CoreSight Trace Macrocells provide all the infrastructure required to debug, monitor, and optimize the performance of a complete System on Chip (SoC) design.   

CoreSight SoC-400 provides configurable versions of all of the CoreSight SoC components with AMBA Designer support for graphical system design and automated IP stitching.

CoreSight SoC components and CPU specific Integration Kits are delivered as part of the CoreSight Design Kits available for each Cortex® CPU.

CoreSight ELA-500 Embedded Logic Analyzer can be connected to ARM IP and 3rd party IP to ensure the fastest Silicon debug by providing low level signal visibility. The ELA-500 can monitor up to 12 groups of up to 128 signals to detect the states leading to lock-ups and data corruption. It provides visibility of CPU load, stores, speculative fetches, cache activity and transaction lifecycle; properties that are not visible with existing ETM trace of instructions.

 

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The CoreSight Infrastructure provides the following capabilities for system-wide trace:

  • Debug and trace visibility of whole systems
  • Cross triggering support between SoC subsystems
  • Multi-source trace in a single stream
  • Standard programmer's models for standard tools support
  • Open interfaces for third party cores
  • Low pin count
  • Low silicon overhead

This enables

  • Higher visibility of complete system operation through fewer pins 
  • Standard solution across all silicon vendors for widest tools support
  • Re-usable for single ARM processor, multi-core or processor and DSP systems
  • Faster time-to-market for more reliable and higher performance products
  • Support of highest frequency processor



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