Enhancing I/O Virtualization
Specialized IP for better system performance
Arm CoreLink system controllers are low-power, high-performance IP cores that perform critical tasks within the Arm AMBA system. CoreLink system controllers are used for Level 3 Cache, DMA, Interrupt, I/O Peripherals and Arm TrustZone, delivering system-critical functions like: I/O Virtualization, Memory management, Cache control.
With the increasing growth of Arm architecture-based SoCs in the infrastructure market, there is a strong need for providing hardware acceleration for critical system functions such as I/O and interrupt management in a virtualized environment. The latest CoreLink 500 series enables support for I/O virtualization using the CoreLink MMU-500 System Memory Management Unit and interrupt management using the CoreLink GIC-500 Generic Interrupt Controller. Both products can be implemented in a way that is scalable, flexible without sacrificing performance.
Designed, tested and validated for optimal compatibility with Arm Cortex processors, Arm Mali multimedia and CoreLink System IP, CoreLink system controllers provide the best way to integrate I/O and peripheral components on the SoC.
System Memory Management Unit
The Arm CoreLink System MMU provides memory management services to SoC bus masters to complement those provided by the Cortex-A series processor family. Enforcing protected memory access while extending memory virtualization services that match those provided by the main application processor, ensures consistent security across the SoC. The CoreLink MMU-500 Memory Management Unit extends hardware-assisted virtualization of the Cortex-A57, Cortex-A53, Cortex-A15 and Cortex-A7 hypervisor mode across all components in the SoC.
Generic Interrupt Controllers
AMBA Interrupt Controllers provide an efficient implementation of the Arm Generic Interrupt Specification to work in multi-processor systems with AHB or AXI interfaces. They are highly configurable to provide the ultimate flexibility in handling a wide range of interrupt sources that can control a single CPU or multiple CPUs.
The Direct Memory Access Controller (DMAC) is a hardware feature that enables movement of blocks of data from peripheral to memory, memory-to-peripheral or memory-to-memory. This movement of data by a separate entity significantly reduces the load on the processor. The AMBA DMA Controllers have been designed to complement both high-end and energy efficient systems. They provide a centralized DMA processing capability that is high performance and highly flexible while at the same time area efficient.
Secure system IP blocks to support the Arm TrustZone system-wide approach to security in preventing access by malicious software to protected memory regions and peripherals such as screens and keypads.
The CoreLink TZC-400 TrustZone Address Space Controller extends on-chip security to protect multiple regions of external memory from software attack. CoreLink TZC-400 adds new fast path to hide look up latency and adds AMBA 4 ACE-Lite/AXI4 support.
Level 2 Cache Controller
CPU to off-chip memory communication has become the performance bottleneck in many SoC. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters.
Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip.
CoreLink Level 2 Cache Controllers, embedded in the CPU or delivered as standalone components, are designed alongside the CPU to match the processor's requirements and easily integrate into AMBA AXI or AHB interconnects.