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CoreLinkインターコネクト

ARM CoreLink Processor System IP

ARM® CoreLink Interconnect provide the components and the methodology for designers to build SoCs based on the AMBA® specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost.

There are three families of interconnect products:

  • CoreLink CCN Cache Coherent Network - Designed for infrastructure applications.
  • CoreLink CCI Cache Coherent Interconnect - Optimized for mobile.
  • CoreLink NIC Network Interconnect - Highly configurable for SoC wide connectivity, multiple applications.

Interconnect improves system performance and reduces power

Massive growth in system integration places on-chip communication and interconnect at the center of system performance. Traffic interactions have become complex and, if left unchecked can cause poor, unpredictable system performance. The CoreLink interconnect family from the home of AMBA is the lowest risk solution for on-chip communication. Designed and tested with ARM Cortex and Mali processors, CoreLink interconnect from ARM provides balanced service for both low latency and high bandwidth data streams. The CoreLink Interconnect family includes three product families; CCN, CCI and NIC. CoreLink CCN Cache Coherent Network enables scalable system coherency in many-core heterogeneous processor systems.

There are 4 products in the CCN family:

CoreLink CCI Cache Coherent Interconnect offers the smallest and lowest power multi-cluster interconnect:

CoreLink NIC Network Interconnect provides a fully configurable, hierarchical, low latency, low power connectivity for AMBA:

Cache Coherency across processors and accelerators

The CoreLink CCN and CCI interconnects provide full coherency between the L2 caches of multicore processors including Cortex-A53 and Cortex-A57, and I/O coherency with other masters such as the Mali GPU, sharing data in L2 caches of the processors. For mobile applications hardware managed cache coherency is a fundamental technology for big.LITTLE processing, allowing the operating system to choose the right processor for the right job. The CoreLink CCI interconnects are design for AMBA 4 ACE and ACE-Lite/AXI4. For infrastructure applications, the CCN family offers scaling from 1 to 48 cores and an integrated configurable L3 cache. The L3 can act as a system cache allowing IO and accelerators to allocate cache memory on chip, offering reduced latency and power by reducing accesses to external memory. The CCN family are optimised for AMBA 5 CHI processors and memory controllers, and AMBA 4 ACE-Lite/AXI4 for IO.

Network features in CoreLink Network Interconnect (NIC-400)

The CoreLink interconnect family delivers key technologies commonly associated with network-on-chip products:

  • Ability to distribute switching and routing functions between many and complex IP blocks
  • Predictability of physical implementation
  • Communication control for system performance optimization
  • Communication visibility for software optimization
  • Reliable integration of complex system containing third party IP core

The CoreLink NIC-400 comes with options for QoS traffic regulation (QoS-400), virtual networks to prevent blocking (QVN-400) and thin links to reduce wiring (TLX-400). The NIC-400 supports long bursts in AXI4 for higher efficiency streaming media and hierarchical clock gating to dramatically reduce idle power.




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