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AMBA用CoreLinkシステム コントローラ

Enhancing I/O virtualization

CoreLink Cache Controllers Image (View Larger CoreLink Cache Controllers Image)ARM® CoreLink™ Controllers for Level 3 Cache, DMA, Interrupt, Peripherals and TrustZone are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with ARM processors, multimedia and System IP, they are the natural complement to the Interconnect and Memory Controller product lines.

The latest CoreLink 500 series enhances I/O virtualization with the CoreLink MMU-500 System Memory Management Unit to complement the hypervisor mode in the Cortex-A57, Cortex-A53, Cortex-A15 and Cortex-A7 with address translation for other masters allowing hardware platforms to support multiple software worlds without modification. As well as the CoreLink GIC-500 Generic Interrupt Controller which handles up to 480 interrupts plus message based interrupts for up to 48 new ARMv8 CPUs across clusters of Cortex-A57 and Cortex-A53 multicore processors.

CoreLink Controllers for Memory, Cache, DMA, TrustZone ® technology and Interrupt Handling

System Memory Management Unit

The CoreLink MMU-500 Memory Management Unit extends hardware-assisted virtualization of the Cortex™-A57, Cortex-A53, Cortex-A15 and Cortex-A7 hypervisor mode across the entire SoC. The MMU-500 translates to physical addresses defined by its TLB that reflects the current CPU context to ensure other masters use consistent memory mapping. Fitting the MMU-500 means drivers no longer require porting for the hypervisor using para-virtualization and raises performance through saving the large para-virtualization software overhead.

The CoreLink MMU-400 Memory Management Unit extends hardware-assisted virtualization of the Cortex-A15 and Cortex-A7.

A number of virtualization use cases are outlined in an ARM System MMU Virtualization whitepaper

Level 2 Cache Controllers

CPU to off-chip memory communication has become the performance bottleneck in many SoC. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters.

Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip.

CoreLink Level 2 Cache Controllers, embedded in the CPU or delivered as standalone components, are designed alongside the CPU to match the processor's requirements and easily integrate into AMBA AXI or AHB interconnects.

DMA Controllers

Efficient use of DMA can significantly improve system performance in multiple dimensions. For example, using a DMA controller can offload a CPU thereby either reducing power or boosting CPU performance (or a combination of both).

The AMBA DMA Controllers have been designed to complement both high-end and energy efficient systems. They provide a centralized DMA processing capability that is high performance and highly flexible while at the same time area efficient.

Interrupt Controllers

AMBA Interrupt Controllers provide an efficient implementation of the ARM Generic Interrupt Specification to work in multi-processor systems with AHB or AXI interfaces. They are highly configurable to provide the ultimate flexibility in handling a wide range of interrupt sources that can control a single CPU or multiple CPUs.

TrustZone Controllers

Three system IP blocks to support the ARM TrustZone system-wide approach to security in preventing access by malicious software to memory regions and peripherals such as keyboards and screens:

  • TrustZone Address Space Controller (TZC-380) to protect code/data in external memory regions
  • TrustZone Protection Controller (BP147) controls the security status of peripherals
  • TrustZone Internal Memory Wrapper (BP141) manages a secure region within the on-chip memory

LCD Controller

A 64-bit Color LCD Controller (PL111) supporting AHB master and slave interfaces and driving TFT, STN, single and dual panel displays.




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