Technology That’s Shaping the Future of Compute
Explore the complete Arm product portfolio, spanning processors, compute subsystems, system IP, and developer tools that power billions of devices worldwide. Each contributes to Arm compute platforms, a secure and scalable foundation for performance, efficiency, and trust.
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System IP
Primecell Micro DMA-230
- Enables efficient block data transfers without CPU intervention to boost system throughput.
- Targets low-power embedded designs with minimal area overhead.
- Reduces processor load to lower power and support scalable SoC performance.
CoreLink DMA-250
- Offloads data movement tasks from the CPU to boost performance and efficiency.
- Scalable channel configuration and trigger options support flexible design trade-offs.
- Integrates TrustZone security to help achieve system-wide secure architectures.
CoreLink DMA-330
- Offloads block data transfers to boost performance and efficiency.
- Highly configurable for scatter-gather, peripheral-to-memory and memory-to-peripheral transfers.
- Supports security, interrupts, and flexible architecture options.
CoreLink DMA-350
- Offloads bulk data transfers to improve performance and reduce power.
- Supports scatter-gather, peripheral-to-memory, and memory-to-peripheral transfers for flexible data movement.
- Optional AXI Stream interfaces and TrustZone security help enable inline processing and secure operation.
CoreLink L2C-310
- Keeps memory access on chip to lower latency and boost system throughput.
- Reduces power by minimizing off-chip memory transactions.
- Designed for easy integration with AMBA AXI or AHB interconnects.
CoreLink CI-700
- Delivers fully coherent system-level cache with filtering to boost memory efficiency.
- Scales from energy-efficient to high-performance implementations.
- Supports AMBA CHI and AMBA AXI protocols.
CMN 600
- Provides a customizable AMBA 5 CHI coherent mesh to optimize system-level data movement.
- Reduces SoC integration complexity with design tools.
- Extends coherent multichip links and agile system cache.
CMN-600AE
- Designed for automotive systems with Safety Ready features.
- Provides a customizable AMBA 5 CHI coherent mesh for high-frequency, non-blocking data transfers.
- Includes tools to reduce SoC integration time and support coherent multichip links.
CMN-700
- Delivers coherent mesh topology for SoCs across infrastructure, storage, HPC, and networking applications.
- Enables coherent multichip links to scale memory and accelerate compute.
- Improves system integration with distributed system cache and fabric customization.
CoreLink NI-710AE
- Scales from low-power to high-performance automotive SoCs.
- Provides ASIL-D safety support.
- Supports AMBA protocols to connect diverse IP blocks.
CCI 550
- Reducing external memory accesses.
- Reducing the software overhead and complexity.
- Enabling use of Arm big.LITTLE processing technology with multiple processor clusters.
CCI-500
- Reduces external memory access.
- Reduces the software overhead and complexity.
- Enables use of Arm big.LITTLE processing technology with multiple processor clusters.
CCI-400
- Reducing external memory accesses.
- Reducing the software overhead.
Network Interconnect
- Scales from simple bridges to complex networks via configurable topology.
- Supports AXI, AHB-Lite, and APB protocols.
- Low-power, low-latency design.
Memory Management Unit
- Provides scalable IO address translation and memory protection.
- Optimized for virtualization in heterogeneous systems.
- Supports multiple MMU variants for varied performance needs.
Generic Interrupt Controller
- Routes and prioritizes interrupts to improve real-time system responsiveness.
- Scales across core counts to support complex multi-core architectures.
- Integrates with Arm processor architectures for standardized interrupt management.
CoreLink PCK-600
- Centralizes clock, reset, and power control to simplify SoC integration.
- Enables dynamic frequency and power management to reduce energy consumption.
- Supports scalable architectures with flexible control and monitoring interfaces.
CoreSight SDC-600
- Centralizes debug authentication and access control across the system.
- Supports secure and non-secure debug flows for production devices.
- Integrates with CoreSight 600 components to simplify SoC debug architecture.
CoreSight SoC-600
- Enables comprehensive debug and trace across CPUs, GPUs, and accelerators.
- Scales with system complexity to support large multi-core designs.
- Simplifies integration with standardized CoreSight architecture and tooling.
CoreSight SoC-600M
- Enables standardized CoreSight debug and trace for Arm based SoCs.
- Supports system-wide visibility with configurable trace and debug components.
- Optimized for low area and power for cost-sensitive embedded designs.
CoreSight SoC-400
- Enables comprehensive debug and trace across processors and system IP.
- Simplifies SoC integration with pre-configured CoreSight components.
- Scales to support complex multi-core and heterogeneous designs.
CoreSight TMC
- Buffers trace in SRAM, FIFO, or system memory for flexible capture options.
- Supports high-bandwidth trace streaming with minimal system impact.
- Integrates with CoreSight debug and trace architectures for scalable designs.
CoreSight STM-500
- Generates software and system events for runtime debug and profiling.
- Supports high-bandwidth trace with minimal performance impact.
- Integrates with CoreSight architectures for scalable system trace.
CoreSight ELA-500
- Captures internal signals without intrusive probes to accelerate system debug.
- Uses programmable comparators and triggers for targeted event analysis.
- Integrates with CoreSight debug and trace for scalable SoC visibility.
CoreSight ELA-600
- Captures internal signals without external probes to reduce debug time.
- Uses advanced comparators and triggers for precise event detection.
- Integrates with CoreSight 600 infrastructure for scalable system visibility.
Arm NoC S3
- Enables flexible topology and QoS to meet diverse bandwidth and latency requirements.
- Optimizes data movement efficiency across processors, accelerators, and memory.
- Simplifies SoC integration with automated configuration and validation tools.
System Interconnect SI 1
- Optimized for minimal latency to support real-time and control workloads.
- Reduces area and power with a lightweight, non-coherent architecture.
- Simplifies integration of processors and peripherals.
CMN S3
- Connects Neoverse CPUs, accelerators, and memory with fully coherent system-level communication.
- Scales across performance points to support networking, storage, and cloud workloads.
- Supports CHI-based coherence and configurable mesh topologies for flexible system design.
CMN S3AE
- Enables fully coherent communication between CPUs, accelerators, and memory.
- Supports Safety Ready architectures aligned with automotive ASIL-B system designs.
- Scales mesh topology and performance for complex automotive workloads.
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