Technology That’s Shaping the Future of Compute

Explore the complete Arm product portfolio, spanning processors, compute subsystems, system IP, and developer tools that power billions of devices worldwide. Each contributes to Arm compute platforms, a secure and scalable foundation for performance, efficiency, and trust.

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The new Arm CPU for next-gen AI data centers
The AI-first Arm CSS Platform for next-gen devices
Fully verified, PPA-optimized, customizable Neoverse compute subsystems
Secure, safety-ready compute for AI-Defined vehicles
Scalable performance and efficiency for mobile AI computing
Supreme performance at optimal power
Powering the most energy-efficient embedded devices
Robust real-time performance
Custom-designed for ultimate performance and specific market needs
Highest performance for machine learning inference
Highest graphics performance for flagship gaming experiences
Next-gen visuals with AI-driven GPU performance.
Higher graphics performance combined with power efficiency
Advanced ISPs for human display and computer vision applications
Scalable and flexible for cloud to edge infrastructure
Powerful solutions for physical security applications
Layered security IP for SoC protection and threat mitigation
Subsystem IP for reduced complexity and faster deployment
Configurable interconnect and system controllers
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System IP

Primecell Micro DMA-230

Arm DMA-230 is a low-gate-count direct memory access controller.
  • Enables efficient block data transfers without CPU intervention to boost system throughput.
  • Targets low-power embedded designs with minimal area overhead.
  • Reduces processor load to lower power and support scalable SoC performance.

CoreLink DMA-250

Arm CoreLink DMA-250 is a configurable AMBA® AHB direct memory access controller.
  • Offloads data movement tasks from the CPU to boost performance and efficiency.
  • Scalable channel configuration and trigger options support flexible design trade-offs.
  • Integrates TrustZone security to help achieve system-wide secure architectures.

CoreLink DMA-330

Arm CoreLink DMA-330 is a direct memory access controller that accelerates data movement.
  • Offloads block data transfers to boost performance and efficiency.
  • Highly configurable for scatter-gather, peripheral-to-memory and memory-to-peripheral transfers.
  • Supports security, interrupts, and flexible architecture options.

CoreLink DMA-350

Arm CoreLink DMA-350 is a direct memory access controller.
  • Offloads bulk data transfers to improve performance and reduce power.
  • Supports scatter-gather, peripheral-to-memory, and memory-to-peripheral transfers for flexible data movement.
  • Optional AXI Stream interfaces and TrustZone security help enable inline processing and secure operation.

CoreLink L2C-310

Arm CoreLink L2C-310 is an AMBA® AXI Level 2 cache controller.
  • Keeps memory access on chip to lower latency and boost system throughput.
  • Reduces power by minimizing off-chip memory transactions.
  • Designed for easy integration with AMBA AXI or AHB interconnects.

CoreLink CI-700

Arm CoreLink CI-700 is a highly configurable, scalable coherent interconnect.
  • Delivers fully coherent system-level cache with filtering to boost memory efficiency.
  • Scales from energy-efficient to high-performance implementations.
  • Supports AMBA CHI and AMBA AXI protocols.

CMN 600

Arm CoreLink CMN-600 is a highly scalable coherent mesh network.
  • Provides a customizable AMBA 5 CHI coherent mesh to optimize system-level data movement.
  • Reduces SoC integration complexity with design tools.
  • Extends coherent multichip links and agile system cache.

CMN-600AE

Arm CoreLink CMN-600AE is a highly scalable coherent mesh interconnect.
  • Designed for automotive systems with Safety Ready features.
  • Provides a customizable AMBA 5 CHI coherent mesh for high-frequency, non-blocking data transfers.
  • Includes tools to reduce SoC integration time and support coherent multichip links.

CMN-700

Arm CoreLink CMN-700 is a scalable coherent mesh network interconnect.
  • Delivers coherent mesh topology for SoCs across infrastructure, storage, HPC, and networking applications.
  • Enables coherent multichip links to scale memory and accelerate compute.
  • Improves system integration with distributed system cache and fabric customization.

CoreLink NI-710AE

Arm CoreLink NI-710AE is a highly configurable, non-coherent, interconnect.
  • Scales from low-power to high-performance automotive SoCs.
  • Provides ASIL-D safety support.
  • Supports AMBA protocols to connect diverse IP blocks.

CCI 550

The CCI-550 is a programmable high-bandwidth interconnect.
  • Reducing external memory accesses.
  • Reducing the software overhead and complexity.
  • Enabling use of Arm big.LITTLE processing technology with multiple processor clusters.

CCI-500

The CCI-500 is a programmable high bandwidth interconnect.
  • Reduces external memory access.
  • Reduces the software overhead and complexity.
  • Enables use of Arm big.LITTLE processing technology with multiple processor clusters.

CCI-400

The CCI-400 combines interconnect and coherency functions into a single module. It supports connectivity for up to two ACE masters.
  • Reducing external memory accesses.
  • Reducing the software overhead.

Network Interconnect

Arm CoreLink NIC is a configurable network interconnect supporting AMBA AXI, AHB-Lite, and APB.
  • Scales from simple bridges to complex networks via configurable topology.
  • Supports AXI, AHB-Lite, and APB protocols.
  • Low-power, low-latency design.

Memory Management Unit

Arm System MMU translates IO addresses and enforces memory protection for SoCs.
  • Provides scalable IO address translation and memory protection.
  • Optimized for virtualization in heterogeneous systems.
  • Supports multiple MMU variants for varied performance needs.

Generic Interrupt Controller

System IP that boosts processor efficiency and interrupt virtualization.
  • Routes and prioritizes interrupts to improve real-time system responsiveness.
  • Scales across core counts to support complex multi-core architectures.
  • Integrates with Arm processor architectures for standardized interrupt management.

CoreLink PCK-600

Arm CoreLink PCK-600 is a programmable clock controller.
  • Centralizes clock, reset, and power control to simplify SoC integration.
  • Enables dynamic frequency and power management to reduce energy consumption.
  • Supports scalable architectures with flexible control and monitoring interfaces.

CoreSight SDC-600

Arm CoreLink SDC-600 is a system debug controller.
  • Centralizes debug authentication and access control across the system.
  • Supports secure and non-secure debug flows for production devices.
  • Integrates with CoreSight 600 components to simplify SoC debug architecture.

CoreSight SoC-600

Arm CoreSight SoC-600 is a scalable debug and trace solution.
  • Enables comprehensive debug and trace across CPUs, GPUs, and accelerators.
  • Scales with system complexity to support large multi-core designs.
  • Simplifies integration with standardized CoreSight architecture and tooling.

CoreSight SoC-600M

Arm CoreSight SoC-600M is a scalable debug and trace solution.
  • Enables standardized CoreSight debug and trace for Arm based SoCs.
  • Supports system-wide visibility with configurable trace and debug components.
  • Optimized for low area and power for cost-sensitive embedded designs.

CoreSight SoC-400

Arm CoreSight SoC-400 is an integrated debug and trace solution.
  • Enables comprehensive debug and trace across processors and system IP.
  • Simplifies SoC integration with pre-configured CoreSight components.
  • Scales to support complex multi-core and heterogeneous designs.

CoreSight TMC

A trace source that enables real-time software instrumentation.
  • Buffers trace in SRAM, FIFO, or system memory for flexible capture options.
  • Supports high-bandwidth trace streaming with minimal system impact.
  • Integrates with CoreSight debug and trace architectures for scalable designs.

CoreSight STM-500

Arm CoreSight STM-500 enables low-overhead software and system trace.
  • Generates software and system events for runtime debug and profiling.
  • Supports high-bandwidth trace with minimal performance impact.
  • Integrates with CoreSight architectures for scalable system trace.

CoreSight ELA-500

Arm CoreSight ELA-500 is an embedded logic analyzer.
  • Captures internal signals without intrusive probes to accelerate system debug.
  • Uses programmable comparators and triggers for targeted event analysis.
  • Integrates with CoreSight debug and trace for scalable SoC visibility.

CoreSight ELA-600

Arm CoreSight ELA-600 is an embedded logic analyzer.
  • Captures internal signals without external probes to reduce debug time.
  • Uses advanced comparators and triggers for precise event detection.
  • Integrates with CoreSight 600 infrastructure for scalable system visibility.

Arm NoC S3

Arm NoC S3 is a configurable, network-on-chip interconnect.
  • Enables flexible topology and QoS to meet diverse bandwidth and latency requirements.
  • Optimizes data movement efficiency across processors, accelerators, and memory.
  • Simplifies SoC integration with automated configuration and validation tools.

System Interconnect SI 1

Arm CoreLink SI-L1 is a system interconnect.
  • Optimized for minimal latency to support real-time and control workloads.
  • Reduces area and power with a lightweight, non-coherent architecture.
  • Simplifies integration of processors and peripherals.

CMN S3

Arm Neoverse CMN S3 is a scalable coherent mesh interconnect.
  • Connects Neoverse CPUs, accelerators, and memory with fully coherent system-level communication.
  • Scales across performance points to support networking, storage, and cloud workloads.
  • Supports CHI-based coherence and configurable mesh topologies for flexible system design.

CMN S3AE

Arm Neoverse CMN S3 (AE) is a scalable coherent mesh interconnect.
  • Enables fully coherent communication between CPUs, accelerators, and memory.
  • Supports Safety Ready architectures aligned with automotive ASIL-B system designs.
  • Scales mesh topology and performance for complex automotive workloads.
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