The configurable AHB Bus Matrix allows the designer to create a optimized multi-layer AHB interconnect. The independent AHB layers allow simultaneous transfers between different masters and slaves which increases system performance. The Bus Matrix includes address decoding per master, and arbitration at each slave. The arbitration can be configured for round robin or priority encoding. The configuration and generation of the AHB Bus Matrix can be driven by a simple Perl script, or from the AMBA Designer tool.
The File Reader Bus Master is a powerful AHB verification component which can drive any bus transfer under the command of a text file. This can be used to test system integration, for example to verify the memory map of a system by reading and writing to peripheral registers.
The full list of components in the AMBA Design Kit:
- Configurable Multi-layer AHB Interconnect
- File Reader Bus master for verification
- Static memory Controller
- Interrupt Controller
- Timers
- Remap and Pause Controller
- Watchdog timer
- Reset Controller
- General Purpose IO (GPIO)
- Example AMBA System (EASY)
- Example Re-try Slave
- Example Bus Master
- Example APB Slave
- AHB Synchronous Bridge
- AHB Asynchronous Bridge
- AHB Synchronous-up Bridge
- AHB Synchronous-down Bridge
- AHB Pass-through Bridge
- AHB-to-APB Bridge
- AHB Downsizer
- Tube verification component for simulation printf
- TIC Box
View the AMBA Design Kit Technical Reference Manual.
For designs using AMBA 3 AXI you should use the AMBA Network Interconnect (NIC-301).
