|
Functionality |
CoreSight Component |
Cortex-M0/Cortex-M0+ | Cortex-M1 | Cortex-M3/Cortex-M4 |
|---|---|---|---|---|
|
Debug |
Debug interface technology | JTAG or Serial Wire Debug with Cortex-M0 DAP For dual mode full CoreSight DAP required |
Dual JTAG & SWD support with CoreSight SWJ-DP | Dual JTAG & SWD support with CoreSight SWJ-DP |
| Memory access while running code | Yes | Yes | Yes | |
| Breakpoint (full) | 4 | 4 | 6 instruction address + 2 literal address | |
| Watchpoint (full) | 2 | 2 | 4 | |
| BKPT instruction | Yes | Yes | Yes | |
|
Trace |
ETM instruction trace | Yes (optional) | ||
| Data Watchpoint & Trace (DWT) | Yes (optional) | |||
| Instrumentation Trace Macrocell (ITM) | Yes (optional) | |||
| Interface to AHB Trace Macrocell | Yes (optional) | |||
| Serial Wire Viewer | Yes (when trace present) | |||
| Trace port |
1 to 4 bit for M3 TPIU, or can use CoreSight TPIU for larger trace port |
|||
| Micro-Trace Buffer | Cortex-M0+ only | No |
