CoreSight technology builds on ARM’s Embedded Trace Macrocells™ (ETM) products, which are widely licensed and supported by the ARM RealView® development tools and over 20 other leading tool vendors.

The CoreSight on-chip debug and trace solution together with the off-chip ARM RealView development tools will provide many benefits to both software developers and silicon manufacturers. For developers, it provides a faster time-to-market; for manufacturers, it has a low pin count, makes their devices more attractive to a product developer and can be leveraged for all cores and complex peripherals.

CoreSight technology consists of the following components:

CoreSight Debug Access Port
This provides real-time access by the debugger software to the JTAG scan chains in the chip, to the AMBA^®   interconnect system and to all debug and trace configuration registers.

External debug access is via the JTAG Debug Port giving access to system resources is via three Access Ports: the AMBA AHB Access Port; the AMBA APB Access Port; and the JTAG Access Port, which provides connection to multiplexed JTAG scan chains. AMBA 3 AXI access is supported with an AHB-AXI bridge (available separately).

CoreSight Embedded Cross Trigger
This provides a standard mechanism for passing debug events between multiple cores, allowing synchronized debug and trace of an entire SoC.

It consists of two main modules: a Cross Trigger Matrix and a Cross Trigger Interface block. The Cross Trigger Interface is generic to any core or controller. A wrapper is provided to adjust the timing and electrical characteristics of signals to ARM cores.

The Cross Trigger Matrix combines the debug events generated by each core sub-system and then broadcasts them to all the other cores in the system via channels. This enables an event on one of the processors to trigger events in other parts of the system.

CoreSight Embedded Trace Macrocells
The CoreSight ETM monitors the core’s internal buses allowing information on the processor’s activity (program and data) to be captured both before and after a specific event, while adding no burden to the processor’s performance and enabling the core to run at full speed.

Powerful software-configurable filters and trigger logic allow the developer to precisely select which instructions and data are captured by the ETM before the information is compressed. The compressed data is either passed directly off-chip through a dedicated, configurable, Trace Port Interface Unit or can be stored in the Embedded Trace Buffer for later read-out. Information from the trace port is then captured by either a logic analyzer or a low-cost trace port analyzer without interrupting, or affecting processor performance.

The CoreSight ETM9^TM and CoreSight ETM11^TM are supplied with ETM JTAG Port and ETM Trace Port blocks for backward compatibility as drop in replacement for older single ETM9 and ETM11RV.

The new Cortex-A8, Cortex-R4 and Cortex-M3  processors are available with CoreSight ETMs. All CoreSight ETMs conform to the new ETMv3 architecture and support cores with TrustZone™, Thumb-2® and Intelligent Energy Manager (IEM).

CoreSight AHB Trace Macrocell
The AMBA AHB^TM Trace Macrocell gives visibility to bus information not inferable for core trace using an ETM such as:

• System performance statistics such as the minimum bus frequency required to support number of transfers, or alternatively any free bus capacity.
• An understanding of multi-layer bus utilization.
• Software debug such as visibility of access to memory areas, and time correlation with CPU program flow and data accesses.

CoreSight Trace Funnel
The CoreSight Trace Funnel is used to combine multiple trace sources into a single bus, called the AMBA Trace Bus (ATB). An arbitration scheme is used to select the input trace stream to pass for each bus cycle.

CoreSight Embedded Trace Buffer
The CoreSight Embedded Trace Buffer™ (ETB) for storing trace data on-chip at high rates and at 32-bit data width. The data can then be read-out at a lower rate - either through the Debug Access Port or by the ARM processor. This provides a solution to get the trace information provided by an ETM or other source off-chip where the number of pins and/or frequency of the required trace port is unacceptable, without the need for an external trace collection unit.

The CoreSight ETB provides a memory interface suitable for compiled SRAM (supplied by the semiconductor manufacturer). The size of the memory is configurable from 4K to 1M bytes, in powers of two.

CoreSight Trace Port Interface Unit
The CoreSight Trace Port Interface Unit formats and transmits trace data off-chip at frequencies asynchronous to the core. The trace data format embeds a source ID into a byte stream to enable multiple trace sources to be transmitted through a single trace port. The trace port is configurable at synthesis and by software to vary the width from 2 to 34 pins and the frequency from 1KHz to the maximum supported by the target process and I/O cell library.

CoreSight Instrumentation Trace Macrocell
The CoreSight Instrumentation Trace Macrocell provides a simple mechanism for debugging real-time systems through a simple memory mapped trace interface. Software running on the ARM processor can write to a block of 32 word registers and this data will be output in to the Trace Funnel for combining with other trace data or alternatively transmitted directly via the Serial Wire Output to the debug tools.

CoreSight Serial Wire Debug
Serial Wire Debug is a two pin, bi-directional data signal plus clock, that replaces the 5/6-pin JTAG interface. The Serial Wire/JTAG Debug Port provides access to system memory peripherals and debug configuration registers.

CoreSight Serial Wire Viewer
The CoreSight Serial Wire Viewer provides an output for Instrumentation Trace through a single pin. The output is unidirectional using Manchester encoding to transmit clock and data over a single wire.

CoreSight Integration Kit
The CoreSight Integration Kit contains RTL test benches, test vectors and full documentation to enable easy validation of connectivity and functionality of the customer specific system implementation of the CoreSight technology. This does not require the use of simulation models of the ARM cores.

High Speed Serial Trace Port
Trace ports are currently parallel data with synchronous clock. Significant pin savings could be achieved through serializing the data and encoding to allow for clock recovery. ARM is currently specifying an interface standard based on existing high speed serial bus technology, see slides in the 'See Also' column at the top right-hand side of this page.

Products available for licensing now:

• ARM CoreSight Design Kit for ARM9 (DK9)
• ARM CoreSight Design Kit for ARM11 (DK11)
• ARM CoreSight Design Kit for Cortex-A8 (DK-A8)
• ARM CoreSight Design Kit for Cortex-R4 (DK-R4)

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