The Core Tile for ARM926EJ-S contains an ARM926EJ-S processor inside a test chip. The processor's configuration signals and a multiplexed AHB bus are connected to the board's headers, so that systems based on this core can be easily prototyped.

A test chip can be clocked at a much faster frequency than an FPGA or simulator model, which enables accelerated software development and debug. 

Core Tiles have the same form factor and headers as Logic Tiles. The Emulation Baseboard is the reference platform for Core Tiles. With a Core Tile and a Logic Tile you can also add an extra ARM processor to the Versatile Platform Baseboard for ARM926EJ-S.

A Core Tile can also be stacked on top of an Integrator/CP baseboard with an Integrator/IM-LT3 Interface Module. This is a simple and flexible way to implement a single-core system.

Example RTL for different configurations of boards is provided with the Core Tile, which accelerates system prototyping and reduces time to market.

Features of the Core Tile for ARM926EJ-S

• ARM926EJ-S processor test chip
• Tile form factor
• High density stacking connectors
• Two PISMO™ connectors for memory expansion boards
• JTAG connection for processor run control and debug (via board below) 
• Mictor connectors for Trace equipment
• Power supply to generate the core voltage
• DACs and ADCs to control the CPU's voltage and measure its power consumption
  

System Performance

The CPU core frequency can be adjusted up to 200MHz, but the maximum frequency depends upon the test-chip fitted. Please refer to the release notes supplied with the board.

Stand-alone Operation

Core Tiles cannot be used stand-alone. They require a motherboard that provides power and a JTAG connector and implements a memory system. For example, a Core Tile and an Emulation Baseboard can be used together for software development and hardware prototyping.

Multi-core Support

Core Tiles cannot be stacked directly on top of each other in order to implement multi-core systems, but require a Logic Tile between every two Core Tiles. The Emulation Baseboard allows two Core Tiles to be stacked on top of it, but FPGA images are not provided for this configuration. Customers can build their own FPGA images by modifying the RTL provided.

You can add cores to the PB926EJ-S baseboard as pairs of Logic Tile and Core Tile.

Java Acceleration

The ARM926EJ-S Core Tile contains ARM Jazelle™ Technology for Java acceleration. To make use of this Java acceleration hardware you will need some software running on the processor which incorporates parts of ARM's Java Technology Enabling Kit (JTEK).

If you are a Sun licensee who has also licensed ARM's JTEK (e.g. an OS vendor) or you are writing applications to run under an operating system, that already incorporates JTEK, then you will have everything you need to develop Java applications. However, if you do not fall into this category, you will be unable to make use of the Java acceleration hardware in the ARM926EJ-S.

Please note:

Core Tiles use ARM test-chips that are specially fabricated to validate new ARM designs and process technologies. These test-chips are provided by a variety of suppliers in small quantities. All test-chips used on Core Tiles are functionally tested by the manufacturer. However, the characteristics of the test-chips used on Core Tiles may vary for different manufacturing batches. ARM, therefore, cannot guarantee that characteristics including but not limited to clock speeds, cache configurations and TCM configurations will be the same from one Core Tile to the next.

Are there any design changes in lead free boards? Lead Free boards design changes