Core Tile for ARM7TDMI

The processor's bus interface and configuration signals are routed to the board's high density connectors, so that systems based on this core can be easily prototyped.

A test chip can be clocked at a faster frequency than a simulation model, which enables accelerated software development and debug. 

The Emulation Baseboard is the reference platform for Core Tiles. With a Core Tile and a Logic Tile you can also add an extra ARM processor to the Versatile Platform Baseboard for ARM926EJ-S.

A Core Tile can also be stacked on top of an Integrator/CP baseboard with an Integrator/IM-LT3 Interface Module. In this case the Integrator/CP provides Flash memory and hardware interfaces such as Ethernet and an audio controller.

Example RTL for different configurations of boards is provided with the Core Tile, which accelerates system prototyping and reduces time to market.

Features of the Core Tile for ARM7TDMI

• ARM7TDMI processor test chip
• Tile form factor
• High density stacking connectors
• Two PISMO™ connectors for memory expansion boards
• JTAG connection for processor run control and debug (via board below) 
• Power supply to generate the core voltage
• DACs and ADCs to control the CPU's voltage and measure its power consumption
  

System Performance

Test chips can normally be run at frequencies above 45MHz, but the maximum CPU core frequency depends upon the test chip fitted on the board and the design of the attached system. The frequency of the system also depends on the maximum speed of the memory system. Please refer to the release notes supplied with the board.

Stand-alone Operation

Core Tiles cannot be used stand-alone. They require a motherboard that implements a memory system and provides power and a JTAG connector . For example, a Core Tile and an Emulation Baseboard can be used together for software development and hardware prototyping.

Multi-core Support

Core Tiles cannot be stacked directly on top of each other in order to implement multi-core systems, but require a Logic Tile between every two Core Tiles. The Emulation Baseboard allows two Core Tiles to be stacked on top of it, but FPGA images are not provided for this configuration. Customers can build their own FPGA images by modifying the RTL provided.

You can add cores to the PB926EJ-S baseboard as pairs of Logic Tile and Core Tile.

Trace

The ARM7TDMI test chip does not contain an Embedded Trace Macrocell (ETM).

Please note:

Core Tiles use ARM test chips that are specially fabricated to validate new ARM designs and process technologies. These test chips are provided by a variety of suppliers in small quantities. All test chips used on Core Tiles are functionally tested by the manufacturer. However, the characteristics of the test chips used on Core Tiles may vary for different manufacturing batches. ARM, therefore, cannot guarantee that characteristics including, but not limited to, clock speeds and revision of the processor will be the same from one Core Tile to the next.