| As part of the family of RealView® Development Boards, Logic Tiles enable system-on-chip (SoC) developers to prototype complete systems, prove custom IP, develop and test device drivers for custom IP. Logic Tiles may be stacked to provide additional capacity. High performance and high pin-count interconnect allows large design prototyping. | 
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Architecture Xilinx Virtex-4 FPGA, XC4VLX160 or XC4VLX200 Versatile tile form factor 3 Programmable clock generators on-tile Compatible with the Emulation Baseboard and the Platform Baseboard for ARM926EJ-S I/O interconnectivity is a super-set of that of the Logic Tiles for Virtex-II FPGAs (LT-XC2V6000 and LT-XC2V8000)
Memory System Because of the limited number of I/O of Virtex-4 FPGAs, the Logic Tile does not contain on-chip RAM The FPGA configuration image is stored in a Flash device. The configuration Flash can store up to 2 FPGA images
I/O Logic Tile Header connectors on top & bottom of each tile 395 interconnect pins to tile above 395 interconnect pins to tile below 128 interconnect pins common to tiles above and below Option to fold over some signals to increase I/O to tile below 8 DIP switches and 8 general purpose LEDs Pushbutton
Power Supply
Scalability Logic Tiles may be stacked Logic Tiles for Virtex-4 devices are mechanically and electrically compatible with Integrator Interface Modules (IM-LT1 and IM-LT3). However, example FPGA images are only provided for the Emulation Baseboard and Platform Baseboard configuration. Logic Tiles interface directly to the Emulation Baseboard and the Platform Baseboard for ARM926EJ-S, without an adapter
FPGA Design Software and Programming Tools |  |  |
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