The RealView® Platform Baseboard for the Cortex-A8 (PB-A8) is the latest addition to the Versatile family of Platform Baseboards.
It is designed to enable ARMv7 architecture applications development and Cortex-A8 processor evaluation. It also supports Operating System porting and custom peripheral driver development. | 
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PB-A8 is Micro ATX, self-powered, supplied in a case
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The Platform Baseboard provides a Cortex-A8 processor at near ASIC speed and a fast AMBA AXI memory system based on standard speed critical peripherals so as to enable software development at near real time.
PB-A8 has a large amount of memory and a rich set of peripherals so as to enable standalone software development without adding further hardware. The baseboard is based on a structured ASIC implementing the AMBA AXI bus infrastructure, AXI memory system and peripherals controllers and a companion FPGA that handle the standard I/O communications.
Logic Tiles can be stacked on top of the Platform Baseboard to provide FPGA space to prototype custom peripherals.
In order to accelerate hardware and software development and reduce time to market the Platform Baseboard is delivered with example RTL, FPGA bit files, and example software that works with all existing Logic Tiles.
ARM Cortex-A8 Test Chip
- Cortex-A8 processor @750MHz
- 32KB L1 I/D Caches, L2 256KB cache with NEON support
Structured ASIC (Northbridge Chip)
- Static Memory Controller (PL354)
- Dynamic Memory Controller (PL340)
- Single Master DMA Controller (PL081)
- Color LCD Controller (PL111)
- AXI Configurable Interconnect (PL300)
- multiplexed AXI interfaces to and from the tile site
- multiplexed AHB-Lite interface to the Southbridge and Debug FPGA
Memory
- 128MB NOR Flash
- 512MB DDR SDRAM
- 2MB Cellular RAM
Baseboard Expansion
- 128MB NOR Flash
- 512MB DDR SDRAM
- 2MB Cellular RAM
- PISMO1TM connector for adding memory modules
- 1 Tile site for custom logic integration with Logic Tiles
- 2x PCI slots and 2x PCI-Express connectors
Standard Frequency
- ARM Cortex-A8 Test chip @ 750MHz
- Internal AXI up to 100MHz
PLDs Programming
- In-built hardware to program the FPGAs and PLDs of the system with a USB cable
- 'progcards' utility for PLDs image selection & downloading
- Configuration JTAG Chain
Debug
- CoreSight debug access port
Peripherals
10/100 Ethernet MAC, High Speed OTG USB v2.0 controller
32-bit 66MHz PCI controller
100MHz 32-bit DDR SDRAM controller
50MHz 32-bit Asynchronous SRAM controller
50MHz 32-bit NOR Flash controller
VGA/DVI, Keyboard and mouse connectors
SmartCard and Multimedia/SD Card controller, Compact Flash Interface
Stereo audio Line in/out and microphone
4 UARTs
Switches, LEDs and GPIO headers
Supported OS and Board Support Packages
Support CD
Example software for all the peripherals on the board except USB is provided with the board or can be obtained from the chipset manufacturer's website.
- Firmware
- System and memory initialization code
- NOR Flash memory read, write and erase code
- Peripheral functional test program
- Network Flash Utility for flash programming from Ethernet
- C library support for stand-alone and semi-hosted images
- Pre-built binaries (little-Endian only)
- Hardware (little-Endian only)
- FPGA Image BIT file for baseboard FPGA
- RTL & bit file for example AXI expansion design on Logic Tiles
- Documentation
