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As part of the family of RealView® Development Boards, Logic Tiles enable system-on-chip (SoC) developers to prototype complete systems, prove custom IP, develop
and test device drivers for custom IP. Logic Tiles may be stacked to provide additional capacity. High performance and high
pin-count interconnect allows large design prototyping.
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Front Back
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Architecture
- Xilinx Virtex-II FPGA, XC2V6000 or XC2V8000
- Versatile tile form factor
- 2 Programmable clock generators on-tile
- Compatible with the Emulation Baseboard and the Platform Baseboard for ARM926EJ-S
- Compatible with Integrator Compact platform (Integrator/CP) using the IM-LT1 Interface Module
Memory System
- Two 32-bit wide 2MB ZBT SSRAM devices per Logic Tile
- 8MB flash memory used for FPGA Configuration Data
I/O
- Logic Tile Header connectors on top & bottom of each tile
- 395 interconnect pins to tile above
- 395 interconnect pins to tile below
- 128 interconnect pins common to tiles above and below
- Option to fold over some signals to increase I/O to tile below
- 4 DIP switches and 4 general purpose LEDs
- Pushbutton
Power Supply
- Logic Tiles require 3.3V and 5V
Scalability
- Logic Tiles may be stacked
- Logic Tiles can be connected to Integrator family boards using the IM-LT1 Interface Module
- Logic Tiles interface directly to the Emulation Baseboard and the Platform Baseboard for ARM926EJ-S, without an adapter
FPGA Design Software and Programming Tools
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