View the Emulation Baseboard usage video (9.3MB Zip File). Once you have downloaded the file, unzip it and run the file 'EB_Video\EB_Video.html' in Internet Explorer. The RealView® Emulation Baseboard is a development board especially designed to prototype systems based on AMBA AXI and AHB bus interfaces, and is the reference platform for systems built around Core Tiles. |  Front Back |
The Emulation Baseboard provides a large amount of memory and peripherals typically used in embedded and wireless applications. The board is based on a large FPGA that normally implements the bus infrastructure, memory system and peripherals controllers, but which can also be used to synthesize small ARM processors. Core Tiles and Logic Tiles can be stacked on top of the Emulation baseboard to implement hardened ARM processors and to provide more FPGA space to prototype custom peripherals. In order to accelerate hardware and software development and reduce time to market the Emulation Baseboard is delivered with example RTL, FPGA bit files, and example software that works with all existing Core Tiles. Baseboard Features and Benefits FPGA - Xilinx Virtex-II XC2V6000
Memory - 64MB Intel NOR Flash
- 256MB 32-bit DDR SDRAM
- 2MB Cellular RAM
- PISMOTM Flash Memory Upgrade Board (available upon request)
- JTAG connector
- In-built hardware to program the FPGAs and PLDs of the system with a USB cable
- Standard frequency: 30MHz AXI or AHB buses
Peripherals - Ethernet
- Connection to Versatile LCD kits
- VGA monitor output
- 4 x Serial ports
- 1 x Synchronous Serial Port
- 16 GPIO pins
- High speed USB OTG and USB Host
- SmartCard
- Keyboard and mouse interfaces
- Multi-Media/SD Card
- Stereo audio in/out and microphone
- 2 line x 16 character LCD
- PCI 32-bit 66MHz host controller
Supported OS and Board Support Packages ARM Embedded Linux is ported to the Emulation Baseboard. Please contact ARM for availability of other OS ports to the Emulation Baseboard. Options - PISMO site
- Two tile sites for expansion with Core Tiles and Logic Tiles
- PCI backplane, 3 slots, clock generation and arbitration
- LCD panel: 2.2" QCIF
Support CD Example software for all the peripherals on the board except USB is provided with the board or can be obtained from the chipset manufacturer's website. - Firmware
- System and memory initialization code
- NOR Flash memory read, write and erase code
- Peripheral functional test program
- C library support for stand-alone and semi-hosted images
- Pre-built binaries (little-endian only)
- Hardware (little-endian only)
- Verilog RTL for baseboard FPGA
- Documentation
Are there any design changes in lead free boards? Lead Free boards design changes | 
