Highly Scalable Mesh for High Performance Automotive Systems

The Arm CoreLink CMN-600AE Coherent Mesh Network is designed for high performance automotive systems for IVI, digital cockpit and ADAS that need to meet ASIL B to ASIL D automotive safety requirements. The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points.


The CoreLink CMN-600AE is part of Arm’s Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.

Features and Benefits

Safety Ready

Designed to meet the automotive safety requirements for building high performance ASIL B to ASIL D systems. Using a highly optimized architecture that implements redundancy while minimizing area using protected shared memories, CMN-600AE provides fault detection and correction features that meet the highest safety requirements for up to ASIL D systems.

High-Performance Scalable Coherent Mesh

The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.

Reduce SoC Integration Time

Socrates guides designers through the configuration and creation of an optimized and viable CoreLink CMN-600AE interconnect fabric. By addressing complex challenges associated with Interconnect configurability and assembly, it helps speed design time and produce a higher quality interconnect.

Coherent Multichip Links

CoreLink CMN-600AE Coherent Multichip Links (CML) extend the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, so system designers can attach more compute or acceleration with a shared virtual memory.

Support for Open Standards

The multichip links also support Cache Coherent Interconnect for Accelerators (CCIX), the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices.

Agile System Cache

Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache is designed to boost high throughput workloads, such as computer vision processing and neural networks.


Arm technology is used in various applications throughout the car including Advanced driver-Assistance Systems (ADAS) and autonomous driving.

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CoreLink GIC-600AE

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CoreLink MMU-600AE

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Architecture and Technologies

A Foundation of Silicon Success

Arm-based chips, device architectures, and technologies orchestrate the performance of everything that makes modern life possible — from smartphones to agricultural sensors and from medical instruments to servers.

CMN-600AE Resources

Everything you need to know to make the right decision for your project. Includes technical documentation, industry insights, and where to go for expert advice.


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