Implementing Neoverse Cores on Advanced FinFET Technology
The broad adoption of cloud services and the rollout of 5G cellular technology has caused an explosion of data. This has expanded computing from the cloud to the edge and endpoints, closer to where the data is captured. This in turn is driving the need for more diverse compute, storage and networking solutions. Neoverse POP IP implementations deliver maximum frequency and performance on advanced FinFET technologies for cloud and HPC workloads as well as maximum performance per watt and efficiency for 5G and edge workloads.
Arm Neoverse and the Arm Ecosystem Provide a Holistic Approach to Design Success
Hyperscale challenges drive the need for custom physical implementation recipes, such as logic placement guides and non-default routing rules (NDR).
- Arm works closely with EDA vendors, such as Cadence and Synopsys, to improve timing correlation between placement and final routing to ensure that the tools are optimizing the "real" critical paths.
- Arm Neoverse POP IP core-hardening acceleration technology enables Arm partners to speed their time to market (TTM) while achieving predictable performance, power, area and cost (PPAC).
- Neoverse POP solutions include fast cache instances (FCIs) with specialized features that address the performance push while offering power efficiency.
- A high-performance logic library includes speed enhanced cells and high drive buffers to enable a Flex-H clock tree for tighter cross-corner correlation. The library also supports very tight power grids to mitigate voltage drop and electro-migration (EM) challenges.
Neoverse V1, N2, and N1 POP implementations are available on 5nm process technology along with physical IP packages to enable PPA-optimized CMN-650 and CMN-700 implementations.
DesignStart Tier of Arm Flexible Access
Approved users can browse, investigate, and download Artisan IP for use in evaluation through manufacturing.