Graphical Micro-Architecture Simulator 

Based on a subset of the Arm®v8-A ISA and now available on GitHub.

The ISA Simulator is a browser-based simulator for a subset of the Armv8-A instructions, (known as LEGv8). It can be run locally on a PC, and is offered exclusively and at no cost to academics, teaching staff, and students worldwide.


Download this visualization tool by clicking the button below which takes you to Arm Education's official GitHub pages.


Note: This tool is currently a BETA version.

Key features and benefits:


  • Easily accessible - web-based and platform neutral, no installation required.
  • Interactive, providing error messages and feedback for insightful learning.
  • Includes a convenient in-built code editor with a visible, interactive register file.
  • Offers multiple execution modes.
  • Uses visual datapaths.
  • Suitable for use with Computer Organization and Design (Arm Edition) by David A. Patterson and John L. Hennessy.


Access Visualization Tool

The Inner Workings of an Arm-Based Microprocessor

A fundamental understanding of an Instruction Set Architecture (ISA) is a crucial skill for all aspiring hardware designers and developers. The ISA acts as the interface between hardware and software, specifying what the instruction set can do and how the processor makes use of those instructions - helping developers write more efficient code.


Sometimes, however, students stuggle to understand how the ISA executes complex commands, for instance for the CPU, databus, memory and I/O.


This simulator simplifies this interaction by allowing students to visualize the instruction execution, establishing a clear link between the inner architecture of a microprocessor and the instructions required to efficiently execute commands on the hardware.

Suggested Areas for Contribution

We’ve made the ISA Simulator open for modification and additions. Contributions are important part or our materials, and our goal is to make it as simple as possible to become a contributor using GitHub.


We invite the academic community to make contributions to the following areas:

  • Further verification and tests to ensure that simulator results are as expected, for example, testcases that include various combinations of LEGv8 instructions.
  • Further improvements to the UI, especially in the pipelined CPU and 'bubble' visualization.
  • Visual display for data memory.
  • Further enhancement to documentation, correcting errors, and providing improvements.
  • Exceptions and cache support.

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