MEDIA ALERT: Strong Industry Momentum Builds For AMBA 4 Coherency Extensions
Since its launch last year, the AMBA® 4 AXI™ Coherency Extensions (ACE™) specification has gained widespread adoption by many of the industry’s leading silicon Partners, with 28 licenses for ARM® Cortex™-A15 and Cortex-A7 processors and 12 licenses for CoreLink™ Cache Coherent Interconnect (CCI-400). Public licensees for CCI-400 include LSI, HiSilicon, STEricsson, Fujitsu and LG.
The AMBA 4 ACE specification enables system level cache coherency across clusters of multicore processors, such as the ARM Cortex-A15 and Cortex-A7 MPCore™ processors and ARM Mali™-T604 graphics processors. This ensures optimum performance and power efficiency of complex heterogeneous SoC designs, and is designed to address next generation computing across mobile, home, networking and gaming applications.
Leading EDA tool vendors are also rapidly bringing new products to market, based on the AMBA ACE specification, that enable faster, more efficient SoC design by these silicon partners. The rich ecosystem of tools using the AMBA 4 protocols allows designers to implement chips with higher system performance and lower power consumption in less time.
Cadence enabled ARM’s lead Cortex-A15 processor licensees to verify their designs on time with the first Verification IP (VIP) support for the full AMBA 4 ACE, ACE-Lite™ and AXI4™ protocol set. “We provide an Interconnect Monitor that in conjunction with the VIP ensures coherency across the full SoC,” said Nick Heaton, Senior Solution Architect, Cadence. “Furthermore, we provide the complete VIP solution with simulated, formal and accelerated VIP for AMBA 4 protocols to serve all phases of verification, including IP block and SoC system level validation.”
Jasper Design Automation's JasperGold® Formal Technology for the AMBA 4 protocols ACE, ACE-Lite, AXI4 and AXI3 facilitates capture of protocol specifications, comprehension, debug, and verification of protocol internal constancy. “Jasper and ARM have worked to develop verification solutions based on formal methods,” said Kathryn Kranen, President and CEO of Jasper Design Automation. “With our technology users can significantly reduce hard to find risks (e.g. discovery of potential deadlocks) as they design and verify IP and SoCs utilizing the AMBA 4 protocols.” Jasper also offers VIP for AMBA 4 ACE, AXI4 and AXI3 that can be used by ARM licensees for the verification of multi-processor-based SoC designs.
Mentor Graphics delivers verification solutions for AMBA 4 protocols that span simulation, formal and emulation with the Questa and Veloce platforms. “Mentor’s verification platforms allow both hardware and software engineers to fully verify their multicore, ARM Cortex processor-based designs using the latest AMBA 4 ACE protocol to address cache coherency issues while they also balance power and performance requirements,” said John Lenyo, VP and GM of the Design Verification Technology division Mentor Graphics. “In addition, Questa VIP provides a verification backbone with ACE, ACE-Lite, AXI4, AXI4-Lite™, AXI4-Stream™, AXI3™ and APB4™ protocol support all conforming to the UVM industry standard for easy adoption into verification flows. This is complemented by Questa inFact intelligent testbench automation technology, one of the industry’s fastest, most productive paths to coverage closure for designs with AMBA 4 bus interfaces.”
Synopsys offers both a full VIP solution and a virtual prototyping for AMBA 4 based systems. “We see rapid adoption of ARM AMBA 4 AXI4 and ACE protocols by our customers designing SoCs based on ARM Cortex-A15 and Cortex-A7 processors,” said John Chilton, senior vice president of Marketing and Business Development at Synopsys. “Our next generation, 100% SystemVerilog, native UVM/VMM/OVM Discovery™ VIP for AMBA4 AXI and ACE standards extends our verification offering for these SoCs with performance, debug, coverage and compliance benefits. Our Virtualizer™ virtual prototyping solution includes ARM Fast Models for Cortex processors and CoreLink CCI-400 cache coherent interconnect to enable early software development for SoCs using AMBA 4 protocols.”
AMBA 4 protocol specifications along with protocol assertions and IP-XACT 1.4 bus definitions are available to all from the ARM website at: http://www.arm.com/products/system-ip/amba/amba-open-specifications.php?tab=Resources.
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