Company Profile

Jasper Design Automation

Company Description

Jasper Design Automation offers innovative solutions, based on formal technologies, for the design and verification of semiconductor IP and SoC. Jasper delivers advanced formal technology, software and services to customers in the global IC markets including consumer, wireless, computing, networking, graphics, and more. Flagship products JasperGold(R), JasperCore (TM), ActiveProp(TM), ActiveDesign(TM) and Intelligent Proof Kits deliver targeted ROI throughout the design cycle. Jasper’s unique technologies provide higher capacity, interactive debug, increased throughput and wider deployment.

ARM recently completed a deployment of Jasper technology and solutions that enhances the validation methodology for ARM® AMBA® protocol-based processors and system IP. Jasper also announced the availability of its suite of system-level VIP for ARM’s ACE-based SoCs. The VIP is the first of its kind for the ACE specification and was a direct result of the tight collaboration between ARM and Jasper for validating the quality and robustness of the specification.

Headquartered in Mountain View, California, Jasper is privately held and has offices and distributors worldwide. Upgrade your verification with Jasper: http://jasper-da.com.

JasperGold® and JasperCoreTM
Advanced Property Verification
JasperGold enables exhaustive and complete verification and provides rapid bug detection as well as end-to-end full proofs of expected design behavior. Its powerful analysis capabilities and ease of use makes it ideal for early-stage bug hunting as well as ensuring the highest confidence possible in design functionality via end-to-end full proofs.

JasperCore promotes economically scalable formal verification. It consists primarily of the formal engines, which fuel the solution, and intelligent resource management schema. JasperCore automatically distributes and manages formal technology across computers, across teams, and across the spectrum of applications.

ActivePropTM
Accelerate Assertion-based Verification
Jasper’s ActiveProp property synthesis increases productivity and reduces time to market by generating assertions, constraints, and covers from RTL and simulation information which can then be used in any assertion-based verification (ABV) flow.

These automatically synthesized properties are intelligent. ActiveProp extracts critical expressions to guide, simplify and merge properties to reduce the number of property candidates the engineer must review. Multiple simulation runs increase the intelligence of synthesized properties. It includes multi-cycle analysis for improved temporal property quality. Properties can be extracted among signals from different modules across different levels of hierarchy.

ActiveDesignTM
Accelerate Design Development and Reuse
ActiveDesign drives higher RTL design quality and designer productivity, reduces verification time, accelerates knowledge transfer, improves design maintenance, and enables efficient design reuse. It delivers early RTL design for debug and verification, as well as enables exploration and reuse of legacy designs and commercial IP. ActiveDesign uses formal analysis, coupled with Jasper's patented Visualize™ technology, to automatically produce interesting waveforms from the (partially-coded) RTL. This is accomplished without the development of a testbench or any input stimulus.

ActiveDesign’s Behavioral Indexing™ technology lets engineers design, concurrently modify, and verify RTL code, then store it in a persistent database containing both the RTL itself and an “index” of its elastic behaviors.

Intelligent Proof Kits
Faster, Accurate Verification of SoC Interface Protocols
Jasper Intelligent Proof Kits enable SoC design teams to accelerate verification by quickly and exhaustively certifying standard protocols including AMBA, AXI and memory controllers. The Proof Kits can be hooked up and configured in the early stages of the design, accelerating RTL development and debug with ActiveDesign™.

They can be used seamlessly with JasperGold® to formally prove the embedded properties, thereby exhaustively verifying that the design meets the protocol specification. Intelligent Proof Kits eliminate the need to manually write properties, which require in-depth understanding of the protocol specification.