Faster Trace Fewer Pins
Ideal for collecting large amounts of trace data where SoC pin count rules out parallel trace. Captures multiple lanes of high-speed serial trace (HSSTP) to enable software analysis.
Features and Benefits
Up to 12.5 Gbps single-lane line rate (60 Gbps combined lane rate) to configure and capture detailed trace information from CoreSight and custom IP devices.
On a single lane – 2 pins - HSSTP can transport trace data at rates comparable to a 16-pin parallel trace port.
Support for Arm HSSTP and Marvell® SETM.
More Features
User I/O port offers scripting capabilities and 8 digital I/O pins to enable automated testing and validation workflows.
Add device specific registers, view instruction and data trace history, customize connections for device-specific registers, bring targets out of reset, and much more.
Code download speeds up to 12 MB per second and JTAG rates up to 180 MHz. SWD rates up to 125MHz can dramatically shorten debug cycles on single or multi-core devices.
Remote gigabit ethernet or USB 3.0 host connections for remote and fast accessibility.
Capture extensive serial trace data supporting up to 6 lanes and 12.5 Gbps. Single-lane line rates stored into an 8GB on-probe trace store.
Works with complex SoC configurations to enable trace data capture for Arm CoreSight Macrocells, such as ETM, PTM, ITM and STM.
Device Bring-up
Develop and debug SoCs and test hardware prior to transferring the optimized software to production hardware.
Firmware Development
Develop and debug firmware such as low-level device drivers that are specifically optimized for different production boards.
OS Level Design
Develop and optimize higher-level code, such as the real-time operating system and applications, so they run within specified parameters.
Instruction Trace Analysis
Fast, deep local trace storage enables use of ETM and PTM to help review execution path for bugs or function-level profiling in Arm Development Studio.