Faster Trace Fewer Pins

Ideal for collecting large amounts of trace data where SoC pin  count rules out parallel trace. Captures multiple lanes of high-speed serial trace (HSSTP) to enable software analysis.

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Features and Benefits
Fast Data Transfer

Up to 12.5 Gbps single-lane line rate (60 Gbps combined lane rate) to configure and capture detailed trace information from CoreSight and custom IP devices. 
Fewer Trace Pins

On a single lane – 2 pins - HSSTP can transport trace data at rates  comparable to a 16-pin parallel trace port. 
Multi-protocol Support

Support for Arm HSSTP and Marvell® SETM.
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Programmable I/O

User I/O port offers scripting capabilities and 8 digital I/O pins to enable automated testing and validation workflows. 

Rich Debug Capabilities

Add device specific registers, view instruction and data trace history, customize connections for device-specific registers, bring targets out of reset, and much more.

Faster Debug

Code download speeds up to 12 MB per second and JTAG rates up to 180 MHz. SWD rates up to 125MHz can dramatically shorten debug cycles on single or multi-core devices.

Remote Debug

Remote gigabit ethernet or USB 3.0 host connections for remote and fast accessibility.

Wide trace bandwidth

Capture extensive serial trace data supporting up to 6 lanes and 12.5 Gbps. Single-lane line rates stored into an 8GB on-probe trace store.

CoreSight Trace Macrocells

Works with complex SoC configurations to enable trace data capture for Arm CoreSight Macrocells, such as ETM, PTM, ITM and STM.

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Use Cases
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Learn how HSSTP can accelerate your SoC development.

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