New ARM CoreLink System IP Provides the Foundation for Next-Generation Heterogeneous SoCs

October 27, 2015

Cambridge, UK, Oct. 27, 2015 – ARM announced new ARM® CoreLink™ system IP designed to enhance system performance and efficiency in next-generation premium mobile devices. The CoreLink CCI-550 interconnect enables ARM big.LITTLE™ processing and a fully coherent GPU while lowering latency and increasing peak throughput. The CoreLink DMC-500 memory controller provides higher bandwidth and latency response for processors and display. Both CoreLink products have been delivered to lead partners and are available for licensing with production silicon expected by late 2016.

"An optimized path to memory is essential for a best-in-class SoC that addresses the demanding mobile market," said Monika Biddulph, general manager, systems and software group, ARM. "IP from ARM is designed in a system context for maximum performance and ease of integration, which is why more than 100 licensees have designed SoCs using trusted ARM system IP. The new CoreLink system IP has ARM and its partners well ahead on the next critical path to increase overall system efficiency and performance in mobile devices."

Acceleration through coherency

The improved support for GPU coherency in CoreLink CCI-550 enhances power management and delivers system-wide advantages. Coherency reduces development costs and time for new applications accelerated by heterogeneous processing for more efficient utilization of compute engines. OpenCL™ 2.0 with shared virtual memory features and other newer programming models take full advantage of system coherency. All processors work on the same data without unnecessary cache maintenance or memory copying. This also enables a system architecture fully aligned with the HSA (Heterogeneous System Architecture) coherency standards.

Scalable for multiple applications and higher throughput

CoreLink CCI-550 includes improvements in the microarchitecture to deliver higher peak throughput for demanding use cases and quality of service (QoS) enhancements that reduce latency by 20 percent. SoC designers can configure the number of memory channels, tracker sizes, snoop filter capacity and scale up to 6 fully coherent processor clusters. The increased scalability addresses a wide range of applications beyond mobile including digital TV, automotive and cost-efficient networking applications.

More bandwidth, less latency

Time and energy-intensive memory transactions require a memory controller designed with a system approach to reduce bottlenecks. For ARM Cortex® processors, CoreLink DMC-500 offers the lowest latency and power along with enhanced QoS for LPDDR4/3 memories operating up to LPDDR4-4267 transfer speeds. When integrated at the design level, CoreLink CCI-550 and CoreLink DMC-500 work together to deliver a peak system memory bandwidth beyond 50GB/s for access to richer content such as 4K video, with predictable performance, leading to the best user experience in premium smartphones and tablets.

"SoC designers must meet ever-increasing performance requirements in flagship mobile devices," said Mike Demler, senior analyst, The Linley Group. "To provide advanced features such as 4K video recording/playback, 120fps cameras, and quad-HD displays, they must integrate heterogeneous CPUs, GPUs, and accelerators into a cache-coherent system while keeping within tight power budgets. ARM's strategy of developing CoreLink system IP, which it co-designs and validates with these processor cores, enables designers to continue raising the bar for mobile computing performance."

Trusted and proven technology

ARM CoreLink interconnect products are a trusted choice for silicon partners and have been licensed more than 200 times by 100-plus silicon partners. ARM delivers system IP that has been extensively system tested and validated with ARM Cortex processors and ARM Mali™ GPUs.



Phil Hughes
+1 512-694-7382
Director of tech PR, ARM  

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