- Applications Processor configuration
- Graphics Processor configuration
- Multi-Layer Bus Architecture
- System-on-Chip debug strategy
- Level 1 and Level 2 Cache sizing
- Memory controller integration.
Significant experience within ARM supports these common building blocks. Active Assist provides access to ARM engineering experience at various project stages, offering a 'best practices' approach to next generation designs.
Active Assist addresses tangible project 'Hot Spots' in a typical SoC design flow:
