Evaluate Arm IP with Precision
Cycle models are 100% cycle accurate models of Arm IP, compiled directly from RTL. With Cycle Models, users can confidently select and configure Arm IP, make architectural decisions, optimize system performance, and develop bare metal software and low-level firmware before silicon is available.
Accelerate system debugging and the implementation of hardware and software changes as you reduce risk by validating hardware implementations that run the actual system software — all while also eliminating a major bottleneck to software development: the availability of a physical hardware prototype.
Cycle Models available 24/7 from Arm’s IP Exchange web portal offer validated IP configuration options (only valid combinations can be chosen). They can be used in Arm SoC Designer, SystemC, and Synopsis Platform Architect MCO to reconfigure, construct, or extend your cycle accurate virtual prototypes.
Built-in rule-checking ensures the accuracy, performance, and flexibility required to enable first-turn SoC success across a wide range of models and formats, including: SystemC models, cycle accurate models compiled by Cycle Model Studio, and Verilog and VHDL co-simulation with leading RTL simulators.
Fast Models are accurate, flexible models of Arm IP that simulate your software running on target hardware, which allow full control of the simulation, including profiling, debug, and trace.
Cycle Model Studio
Cycle Model Studio lets you leverage existing IP, either from previous projects or a third party to generate custom Cycle Models and jumpstart creation of a complete and accurate virtual prototype.
Cycle Performance Analysis Kits
CPAKs are virtual SoC prototypes complete with software, consisting of 100% cycle accurate technology models connected with System IP Cycle Models, so you can get up and running right away.
Arm Development Studio
An end-to-end software development environment for all Arm-based systems, including Arm Compiler, debuggers, IDEs, performance analysis tools, models and middleware.