Evaluate Arm IP with Precision

Cycle models are 100% cycle accurate models of Arm IP, compiled directly from RTL. With Cycle Models, users can confidently select and configure Arm IP, make architectural decisions, optimize system performance, and develop bare metal software and low-level firmware before silicon is available.

Evaluate Cycle Models
Features and Benefits
A Golden IP Performance Reference

100% accurate cycle models of Cortex processors and system IP, including NIC, CCI, CCN, and CMN interconnect.  Prove your assumptions before committing to hardware. Analyze complex interconnect behavior, quickly explore design options, and see the impact of hardware/software tradeoffs.

Rapid System Level Debugging

Cycle Models are instrumented to enable fast and detailed debug and analysis of Arm IP whether under software workloads or traffic-based stimulus. Arm debugger integration, and cache coherent memory views are all available to SoC architects, system designers, performance engineers, and programmers.

Unified Software and Hardware Analysis

Software teams can view code, set breakpoints, and examine registers and memories. Hardware teams can examine signals, dump waveforms, and trace execution through the system. All users gain rapid insight from instrumented architectural and microarchitectural registers and a performance monitoring unit.

More Features
Reduced Design Risk

Accelerate system debugging and the implementation of hardware and software changes as you reduce risk by validating hardware implementations that run the actual system software — all while also eliminating a major bottleneck to software development: the availability of a physical hardware prototype.

Flexible and Extensible

Cycle Models available 24/7 from Arm’s IP Exchange web portal offer validated IP configuration options (only valid combinations can be chosen). They can be used in Arm SoC Designer, SystemC, and Synopsis Platform Architect MCO to reconfigure, construct, or extend your cycle accurate virtual prototypes. 

Powerful Easy-to-Use GUI

Built-in rule-checking ensures the accuracy, performance, and flexibility required to enable first-turn SoC success across a wide range of models and formats, including: SystemC models, cycle accurate models compiled by Cycle Model Studio, and Verilog and VHDL co-simulation with leading RTL simulators. 

Use Cases

Get a head start on developing your SoC by evaluating Arm IP, optimizing system performance, and validating low-level code prior to silicon availability.

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Learn how Arm Cycle Models can accelerate your SoC development.

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